Microchip Technology ARD00330 データシート
PIC18F87J72 FAMILY
DS39979A-page 422
Preliminary
2010 Microchip Technology Inc.
FIGURE 29-19:
A/D CONVERSION TIMING
TABLE 29-25: A/D CONVERSION REQUIREMENTS
Param
No.
Symbol
Characteristic
Min
Max
Units
Conditions
130
T
AD
A/D Clock Period
0.8
12.5
(1)
s
T
OSC
based, V
REF
3.0V
131
T
CNV
Conversion Time
(not including acquisition time)
(not including acquisition time)
(2)
13
14
T
AD
132
T
ACQ
Acquisition Time
(3)
1.4
—
s
135
T
SWC
Switching Time from Convert
Sample
—
(Note 4)
137
T
DIS
Discharge Time
0.2
—
s
Note 1: The time of the A/D clock period is dependent on the device frequency and the T
AD
clock divider.
2: ADRES registers may be read on the following T
CY
cycle.
3: The time for the holding capacitor to acquire the “New” input voltage when the voltage changes full scale
after the conversion (V
DD
to V
SS
or V
SS
to V
DD
). The source impedance (R
S
) on the input channels is 50
.
4: On the following cycle of the device clock.
131
130
132
BSF ADCON0, GO
Q4
A/D CLK
(1)
A/D DATA
ADRES
ADIF
GO
SAMPLE
OLD_DATA
SAMPLING STOPPED
DONE
NEW_DATA
(Note 2)
11
10
9
3
2
1
Note 1:
If the A/D clock source is selected as RC, a time of T
CY
is added before the A/D clock starts. This allows the SLEEP instruction
to be executed.
2:
This is a minimal RC delay (typically 100 ns), which also disconnects the holding capacitor from the analog input.
. . .
. . .
T
CY
0