Microchip Technology ARD00330 データシート
2010 Microchip Technology Inc.
Preliminary
DS39979A-page 43
PIC18F87J72 FAMILY
5.0
RESET
The PIC18F87J72 family of devices differentiates
between various kinds of Reset:
• Power-on Reset (POR)
• MCLR Reset during normal operation
• MCLR Reset during power-managed modes
• Watchdog Timer (WDT) Reset (during
between various kinds of Reset:
• Power-on Reset (POR)
• MCLR Reset during normal operation
• MCLR Reset during power-managed modes
• Watchdog Timer (WDT) Reset (during
execution)
• Brown-out Reset (BOR)
• Configuration Mismatch (CM)
• RESET Instruction
• Stack Full Reset
• Stack Underflow Reset
This section discusses Resets generated by MCLR,
POR and BOR, and covers the operation of the various
start-up timers. Stack Reset events are covered in
Section 6.1.4.4 “Stack Full and Underflow Resets”.
WDT Resets are covered in Section 26.2 “Watchdog
Timer (WDT)”.
A simplified block diagram of the on-chip Reset circuit
is shown in Figure 5-1.
• Configuration Mismatch (CM)
• RESET Instruction
• Stack Full Reset
• Stack Underflow Reset
This section discusses Resets generated by MCLR,
POR and BOR, and covers the operation of the various
start-up timers. Stack Reset events are covered in
Section 6.1.4.4 “Stack Full and Underflow Resets”.
WDT Resets are covered in Section 26.2 “Watchdog
Timer (WDT)”.
A simplified block diagram of the on-chip Reset circuit
is shown in Figure 5-1.
5.1
RCON Register
Device Reset events are tracked through the RCON
register (Register 5-1). The lower five bits of the
register indicate that a specific Reset event has
occurred. In most cases, these bits can only be set by
the event and must be cleared by the application after
the event. The state of these flag bits, taken together,
can be read to indicate the type of Reset that just
occurred. This is described in more detail in
Section 5.7 “Reset State of Registers”.
The RCON register also has a control bit for setting
interrupt priority (IPEN). Interrupt priority is discussed
in Section 9.0 “Interrupts”.
register (Register 5-1). The lower five bits of the
register indicate that a specific Reset event has
occurred. In most cases, these bits can only be set by
the event and must be cleared by the application after
the event. The state of these flag bits, taken together,
can be read to indicate the type of Reset that just
occurred. This is described in more detail in
Section 5.7 “Reset State of Registers”.
The RCON register also has a control bit for setting
interrupt priority (IPEN). Interrupt priority is discussed
in Section 9.0 “Interrupts”.
FIGURE 5-1:
SIMPLIFIED BLOCK DIAGRAM OF ON-CHIP RESET CIRCUIT
S
R
Q
External Reset
MCLR
V
DD
WDT
Time-out
V
DD
Rise
Detect
PWRT
INTRC
POR Pulse
PWRT
Chip_Reset
11-Bit Ripple Counter
Brown-out
Reset
(1)
RESET
Instruction
Stack
Pointer
Stack Full/Underflow Reset
Sleep
IDLE
65.5 ms (typical)
Note 1: The ENVREG pin must be tied high to enable Brown-out Reset. The Brown-out Reset is provided by the on-chip
voltage regulator when there is insufficient source voltage to maintain regulation.
Configuration Word
Mismatch
32
s (typical)