Microchip Technology ARD00330 データシート
2010 Microchip Technology Inc.
Preliminary
DS39979A-page 465
PIC18F87J72 FAMILY
INDEX
A
A/D
A/D Converter Interrupt, Configuring ........................ 277
Acquisition Requirements ......................................... 278
ADCAL Bit................................................................. 281
ADCON0 Register..................................................... 273
ADCON1 Register..................................................... 273
ADCON2 Register..................................................... 273
ADRESH Register............................................. 273, 276
ADRESL Register ..................................................... 273
Analog Port Pins, Configuring................................... 279
Associated Registers ................................................ 281
Configuring the Module............................................. 277
Conversion Clock (T
Acquisition Requirements ......................................... 278
ADCAL Bit................................................................. 281
ADCON0 Register..................................................... 273
ADCON1 Register..................................................... 273
ADCON2 Register..................................................... 273
ADRESH Register............................................. 273, 276
ADRESL Register ..................................................... 273
Analog Port Pins, Configuring................................... 279
Associated Registers ................................................ 281
Configuring the Module............................................. 277
Conversion Clock (T
Conversion Status (GO/DONE Bit) ........................... 276
Conversions .............................................................. 280
Converter Calibration ................................................ 281
Converter Characteristics ......................................... 421
Operation in Power-Managed Modes ....................... 281
Overview ................................................................... 273
Selecting and Configuring Automatic
Conversions .............................................................. 280
Converter Calibration ................................................ 281
Converter Characteristics ......................................... 421
Operation in Power-Managed Modes ....................... 281
Overview ................................................................... 273
Selecting and Configuring Automatic
Absolute Maximum Ratings .............................................. 389
AC (Timing) Characteristics .............................................. 404
AC (Timing) Characteristics .............................................. 404
Parameter Symbology .............................................. 404
Temperature and Voltage Specifications .................. 405
Timing Conditions ..................................................... 405
Temperature and Voltage Specifications .................. 405
Timing Conditions ..................................................... 405
ACKSTAT ......................................................................... 229
ACKSTAT Status Flag ...................................................... 229
ADCAL Bit......................................................................... 281
ADCON0 Register............................................................. 273
ACKSTAT Status Flag ...................................................... 229
ADCAL Bit......................................................................... 281
ADCON0 Register............................................................. 273
ADCON1 Register............................................................. 273
ADCON2 Register............................................................. 273
ADDFSR ........................................................................... 377
ADDLW ............................................................................. 340
Addressable Universal Synchronous Asynchronous
ADCON2 Register............................................................. 273
ADDFSR ........................................................................... 377
ADDLW ............................................................................. 340
Addressable Universal Synchronous Asynchronous
Receiver Transmitter (AUSART). See AUSART.
ADDULNK......................................................................... 377
ADDWF ............................................................................. 340
ADDWFC .......................................................................... 341
ADRESH Register............................................................. 273
ADRESL Register ..................................................... 273, 276
AFE
ADDWF ............................................................................. 340
ADDWFC .......................................................................... 341
ADRESH Register............................................................. 273
ADRESL Register ..................................................... 273, 276
AFE
Analog Inputs ............................................................ 284
Block Diagram........................................................... 435
Boost Mode............................................................... 444
Data Ready Pin (DR) ................................................ 454
Delta-Sigma ADC Architecture ................................. 284
Block Diagram........................................................... 435
Boost Mode............................................................... 444
Data Ready Pin (DR) ................................................ 454
Delta-Sigma ADC Architecture ................................. 284
Delta-Sigma Modulator ............................................. 444
Electrical Characteristics................................... 423–425
External Voltage Reference ...................................... 447
Internal Clock Chain.................................................. 449
Internal Registers...................................................... 456
Internal Voltage Reference ............................... 284, 447
Output Coding........................................................... 445
Output Data Rates (table) ......................................... 439
Phase Delay Block............................................ 284, 448
Electrical Characteristics................................... 423–425
External Voltage Reference ...................................... 447
Internal Clock Chain.................................................. 449
Internal Registers...................................................... 456
Internal Voltage Reference ............................... 284, 447
Output Coding........................................................... 445
Output Data Rates (table) ......................................... 439
Phase Delay Block............................................ 284, 448
Power-On Reset ....................................................... 447
Programmable Gain Amplifiers................................. 284
Register Map .................................................... 285, 456
Registers
Programmable Gain Amplifiers................................. 284
Register Map .................................................... 285, 456
Registers
CONFIG1.......................................................... 462
CONFIG2.......................................................... 463
DATA_CHn....................................................... 457
GAIN................................................................. 459
PHASE ............................................................. 458
STATUS/COM .................................................. 461
CONFIG2.......................................................... 463
DATA_CHn....................................................... 457
GAIN................................................................. 459
PHASE ............................................................. 458
STATUS/COM .................................................. 461
Required Connections .............................................. 287
Resolution................................................................. 446
Serial Interface ................................................. 286, 449
Resolution................................................................. 446
Serial Interface ................................................. 286, 449
Terminology...................................................... 438–443
Using ........................................................................ 288
Voltage Reference.................................................... 447
Using ........................................................................ 288
Voltage Reference.................................................... 447
Analog-to-Digital Converter. See A/D.
ANDLW............................................................................. 341
ANDWF............................................................................. 342
Assembler
ANDLW............................................................................. 341
ANDWF............................................................................. 342
Assembler
AUSART
Associated Registers, Receive......................... 267
Associated Registers, Transmit........................ 265
Receiver ........................................................... 266
Setting up 9-Bit Mode with
Associated Registers, Transmit........................ 265
Receiver ........................................................... 266
Setting up 9-Bit Mode with
Associated Registers........................................ 262
Baud Rate Error, Calculating............................ 262
Baud Rates, Asynchronous Modes .................. 263
High Baud Rate Select (BRGH Bit) .................. 262
Operation in Power-Managed Modes............... 262
Sampling .......................................................... 262
Baud Rate Error, Calculating............................ 262
Baud Rates, Asynchronous Modes .................. 263
High Baud Rate Select (BRGH Bit) .................. 262
Operation in Power-Managed Modes............... 262
Sampling .......................................................... 262
Associated Registers, Receive......................... 270
Associated Registers, Transmit........................ 269
Reception ......................................................... 270
Transmission .................................................... 268
Associated Registers, Transmit........................ 269
Reception ......................................................... 270
Transmission .................................................... 268
Associated Registers, Receive......................... 272
Associated Registers, Transmit........................ 271
Reception ......................................................... 272
Transmission .................................................... 271
Associated Registers, Transmit........................ 271
Reception ......................................................... 272
Transmission .................................................... 271
B
Baud Rate Generator ....................................................... 225
BC..................................................................................... 342
BCF .................................................................................. 343
BF ..................................................................................... 229
BF Status Flag.................................................................. 229
Bias Generation (LCD)
BC..................................................................................... 342
BCF .................................................................................. 343
BF ..................................................................................... 229
BF Status Flag.................................................................. 229
Bias Generation (LCD)
Block Diagrams
A/D............................................................................ 276
AFE, Required Connections ..................................... 287
Analog Input Model................................................... 277
AUSART Receive ..................................................... 266
AUSART Transmit .................................................... 264
AFE, Required Connections ..................................... 287
Analog Input Model................................................... 277
AUSART Receive ..................................................... 266
AUSART Transmit .................................................... 264