Microchip Technology ARD00330 データシート

PIC18F87J72 FAMILY

DS39979A-page 50

Preliminary

 2010 Microchip Technology Inc.

FSR1H

PIC18F8XJ72

---- xxxx

---- uuuu

FSR1L

PIC18F8XJ72

xxxx xxxx

uuuu uuuu

BSR

PIC18F8XJ72

---- 0000

---- uuuu

INDF2

PIC18F8XJ72

N/A

POSTINC2

PIC18F8XJ72

N/A

POSTDEC2

PIC18F8XJ72

N/A

PREINC2

PIC18F8XJ72

N/A

PLUSW2

PIC18F8XJ72

N/A

FSR2H

PIC18F8XJ72

---- xxxx

---- uuuu

FSR2L

PIC18F8XJ72

xxxx xxxx

uuuu uuuu

STATUS

PIC18F8XJ72

---x xxxx

---u uuuu

TMR0H

PIC18F8XJ72

0000 0000

uuuu uuuu

TMR0L

PIC18F8XJ72

xxxx xxxx

uuuu uuuu

T0CON

PIC18F8XJ72

1111 1111

uuuu uuuu

OSCCON

PIC18F8XJ72

0110 q000

uuuu quuu

LCDREG

PIC18F8XJ72

-011 1100

-011 1000

-uuu uuuu

WDTCON

PIC18F8XJ72

0--- ---0

u--- ---u

RCON

(4)

PIC18F8XJ72

0-11 11q0

0-0q qquu

u-uu qquu

TMR1H

PIC18F8XJ72

xxxx xxxx

uuuu uuuu

TMR1L

PIC18F8XJ72

xxxx xxxx

uuuu uuuu

T1CON

PIC18F8XJ72

0000 0000

u0uu uuuu

uuuu uuuu

TMR2

PIC18F8XJ72

0000 0000

uuuu uuuu

PR2

PIC18F8XJ72

1111 1111

T2CON

PIC18F8XJ72

-000 0000

-uuu uuuu

SSPBUF

PIC18F8XJ72

xxxx xxxx

uuuu uuuu

SSPADD

PIC18F8XJ72

0000 0000

uuuu uuuu

SSPSTAT

PIC18F8XJ72

0000 0000

uuuu uuuu

SSPCON1

PIC18F8XJ72

0000 0000

uuuu uuuu

SSPCON2

PIC18F8XJ72

0000 0000

uuuu uuuu

TABLE 5-2:

INITIALIZATION CONDITIONS FOR ALL REGISTERS (CONTINUED)

Register

Applicable

Devices

Power-on Reset,

Brown-out Reset

MCLR Resets

WDT Reset

RESET Instruction

Stack Resets

Wake-up via WDT

or Interrupt

Legend: u = unchanged, x = unknown, - = unimplemented bit, read as ‘0’, q = value depends on condition.

Shaded cells indicate conditions do not apply for the designated device.

Note 1: When the wake-up is due to an interrupt and the GIEL or GIEH bit is set, the TOSU, TOSH and TOSL are

updated with the current value of the PC. The STKPTR is modified to point to the next location in the
hardware stack.

2: When the wake-up is due to an interrupt and the GIEL or GIEH bit is set, the PC is loaded with the

interrupt vector (0008h or 0018h).

3: One or more bits in the INTCONx or PIRx registers will be affected (to cause wake-up).
4: See Table 5-1 for Reset value for specific condition.
5: Bits 6 and 7 of PORTA, LATA and TRISA are enabled depending on the oscillator mode selected. When

not enabled as PORTA pins, they are disabled and read as ‘0’.