Microchip Technology DV164136 データシート
2007-2012 Microchip Technology Inc.
DS39778E-page 117
PIC18F87J11 FAMILY
9.0
8 x 8 HARDWARE MULTIPLIER
9.1
Introduction
All PIC18 devices include an 8 x 8 hardware multiplier
as part of the ALU. The multiplier performs an unsigned
operation and yields a 16-bit result that is stored in the
product register pair, PRODH:PRODL. The multiplier’s
operation does not affect any flags in the STATUS
register.
Making multiplication a hardware operation allows it to
be completed in a single instruction cycle. This has the
advantages of higher computational throughput and
reduced code size for multiplication algorithms and
allows the PIC18 devices to be used in many applica-
tions previously reserved for digital signal processors.
A comparison of various hardware and software
multiply operations, along with the savings in memory
and execution time, is shown in
as part of the ALU. The multiplier performs an unsigned
operation and yields a 16-bit result that is stored in the
product register pair, PRODH:PRODL. The multiplier’s
operation does not affect any flags in the STATUS
register.
Making multiplication a hardware operation allows it to
be completed in a single instruction cycle. This has the
advantages of higher computational throughput and
reduced code size for multiplication algorithms and
allows the PIC18 devices to be used in many applica-
tions previously reserved for digital signal processors.
A comparison of various hardware and software
multiply operations, along with the savings in memory
and execution time, is shown in
9.2
Operation
shows the instruction sequence for an 8 x 8
unsigned multiplication. Only one instruction is required
when one of the arguments is already loaded in the
WREG register.
when one of the arguments is already loaded in the
WREG register.
shows the sequence to do an 8 x 8 signed
multiplication. To account for the sign bits of the argu-
ments, each argument’s Most Significant bit (MSb) is
tested and the appropriate subtractions are done.
ments, each argument’s Most Significant bit (MSb) is
tested and the appropriate subtractions are done.
EXAMPLE 9-1:
8 x 8 UNSIGNED
MULTIPLY ROUTINE
MULTIPLY ROUTINE
EXAMPLE 9-2:
8 x 8 SIGNED MULTIPLY
ROUTINE
ROUTINE
TABLE 9-1:
PERFORMANCE COMPARISON FOR VARIOUS MULTIPLY OPERATIONS
MOVF
ARG1, W
;
MULWF
ARG2
; ARG1 * ARG2 ->
; PRODH:PRODL
MOVF
ARG1, W
MULWF
ARG2
; ARG1 * ARG2 ->
; PRODH:PRODL
BTFSC
ARG2, SB
; Test Sign Bit
SUBWF
PRODH, F
; PRODH = PRODH
; - ARG1
MOVF
ARG2, W
BTFSC
ARG1, SB
; Test Sign Bit
SUBWF
PRODH, F
; PRODH = PRODH
; - ARG2
Routine
Multiply Method
Program
Memory
(Words)
Cycles
(Max)
Time
@ 48 MHz
@ 10 MHz
@ 4 MHz
8 x 8 unsigned
Without hardware multiply
13
69
5.7
s
27.6
s
69
s
Hardware multiply
1
1
83.3 ns
400 ns
1
s
8 x 8 signed
Without hardware multiply
33
91
7.5
s
36.4
s
91
s
Hardware multiply
6
6
500 ns
2.4
s
6
s
16 x 16 unsigned
Without hardware multiply
21
242
20.1
s
96.8
s
242
s
Hardware multiply
28
28
2.3
s
11.2
s
28
s
16 x 16 signed
Without hardware multiply
52
254
21.6
s
102.6
s
254
s
Hardware multiply
35
40
3.3
s
16.0
s
40
s