Microchip Technology MA240017 データシート
2008-2011 Microchip Technology Inc.
DS39927C-page 151
PIC24F16KA102 FAMILY
bit 3
BRGH:
High Baud Rate Enable bit
1
= BRG generates 4 clocks per bit period (4x baud clock, High-Speed mode)
0
= BRG generates 16 clocks per bit period (16x baud clock, Standard mode)
bit 2-1
PDSEL<1:0>:
Parity and Data Selection bits
11
= 9-bit data, no parity
10
= 8-bit data, odd parity
01
= 8-bit data, even parity
00
= 8-bit data, no parity
bit 0
STSEL:
Stop Bit Selection bit
1
= Two Stop bits
0
= One Stop bit
REGISTER 18-1:
UxMODE: UARTx MODE REGISTER (CONTINUED)
Note 1:
This feature is only available for the 16x BRG mode (BRGH = 0).
2:
Bit availability depends on pin availability.