Microchip Technology MA330031-2 データシート
dsPIC33EPXXXGP50X, dsPIC33EPXXXMC20X/50X AND PIC24EPXXXGP/MC20X
DS70000657H-page 28
2011-2013 Microchip Technology Inc.
C1IN1-
C1IN2-
C1IN1+
OA1OUT
C1OUT
C1IN2-
C1IN1+
OA1OUT
C1OUT
I
I
I
I
I
O
O
O
Analog
Analog
Analog
Analog
Analog
Analog
Analog
—
No
No
No
No
No
No
No
Yes
Op Amp/Comparator 1 Negative Input 1.
Comparator 1 Negative Input 2.
Op Amp/Comparator 1 Positive Input 1.
Op Amp 1 output.
Comparator 1 output.
Comparator 1 Negative Input 2.
Op Amp/Comparator 1 Positive Input 1.
Op Amp 1 output.
Comparator 1 output.
C2IN1-
C2IN2-
C2IN1+
OA2OUT
C2OUT
C2IN2-
C2IN1+
OA2OUT
C2OUT
I
I
I
I
I
O
O
O
Analog
Analog
Analog
Analog
Analog
Analog
Analog
—
No
No
No
No
No
No
No
Yes
Op Amp/Comparator 2 Negative Input 1.
Comparator 2 Negative Input 2.
Op Amp/Comparator 2 Positive Input 1.
Op Amp 2 output.
Comparator 2 output.
Comparator 2 Negative Input 2.
Op Amp/Comparator 2 Positive Input 1.
Op Amp 2 output.
Comparator 2 output.
C3IN1-
C3IN2-
C3IN1+
OA3OUT
C3OUT
C3IN2-
C3IN1+
OA3OUT
C3OUT
I
I
I
I
I
O
O
O
Analog
Analog
Analog
Analog
Analog
Analog
Analog
—
No
No
No
No
No
No
No
Yes
Op Amp/Comparator 3 Negative Input 1.
Comparator 3 Negative Input 2.
Op Amp/Comparator 3 Positive Input 1.
Op Amp 3 output.
Comparator 3 output.
Comparator 3 Negative Input 2.
Op Amp/Comparator 3 Positive Input 1.
Op Amp 3 output.
Comparator 3 output.
C4IN1-
C4IN1+
C4OUT
C4IN1+
C4OUT
I
I
I
O
Analog
Analog
Analog
—
No
No
No
Yes
Comparator 4 Negative Input 1.
Comparator 4 Positive Input 1.
Comparator 4 output.
Comparator 4 Positive Input 1.
Comparator 4 output.
CV
REF1O
CV
REF2O
O
O
O
Analog
Analog
Analog
No
No
No
Op amp/comparator voltage reference output.
Op amp/comparator voltage reference divided by 2 output.
Op amp/comparator voltage reference divided by 2 output.
PGED1
PGEC1
PGED2
PGEC2
PGED3
PGEC3
PGEC1
PGED2
PGEC2
PGED3
PGEC3
I/O
I
I/O
I
I/O
I
ST
ST
ST
ST
ST
ST
ST
ST
ST
ST
ST
No
No
No
No
No
No
No
No
No
No
No
Data I/O pin for Programming/Debugging Communication Channel 1.
Clock input pin for Programming/Debugging Communication Channel 1.
Data I/O pin for Programming/Debugging Communication Channel 2.
Clock input pin for Programming/Debugging Communication Channel 2.
Data I/O pin for Programming/Debugging Communication Channel 3.
Clock input pin for Programming/Debugging Communication Channel 3.
Clock input pin for Programming/Debugging Communication Channel 1.
Data I/O pin for Programming/Debugging Communication Channel 2.
Clock input pin for Programming/Debugging Communication Channel 2.
Data I/O pin for Programming/Debugging Communication Channel 3.
Clock input pin for Programming/Debugging Communication Channel 3.
MCLR
I/P
ST
No Master Clear (Reset) input. This pin is an active-low Reset to the
device.
AV
DD
P
P
No Positive supply for analog modules. This pin must be connected at all
times.
AV
SS
P
P
No Ground reference for analog modules. This pin must be connected at all
times.
V
DD
P
—
No Positive supply for peripheral logic and I/O pins.
V
CAP
P
—
No CPU logic filter capacitor connection.
V
SS
P
—
No Ground reference for logic and I/O pins.
V
REF
+
I
Analog
No Analog voltage reference (high) input.
V
REF
-
I
Analog
No Analog voltage reference (low) input.
TABLE 1-1:
PINOUT I/O DESCRIPTIONS (CONTINUED)
Pin Name
(
4
)
Pin
Type
Buffer
Type
PPS
Description
Legend:
CMOS = CMOS compatible input or output
Analog = Analog input
P = Power
ST = Schmitt Trigger input with CMOS levels
O = Output
I = Input
PPS = Peripheral Pin Select
TTL = TTL input buffer
Note 1:
This pin is available on dsPIC33EPXXXMC20X/50X and PIC24EPXXXMC20X devices only.
2:
This pin is available on dsPIC33EPXXXGP/MC50X devices only.
3:
This is the default Fault on Reset for dsPIC33EPXXXMC20X/50X and PIC24EPXXXMC20X devices. See
Section 16.0 “High-Speed PWM Module (dsPIC33EPXXXMC20X/50X and PIC24EPXXXMC20X
Devices Only)”
Devices Only)”
for more information.
4:
Not all pins are available in all packages variants. See the
“Pin Diagrams”
section for pin availability.
5:
There is an internal pull-up resistor connected to the TMS pin when the JTAG interface is active. See the
JTAGEN bit field in
JTAGEN bit field in
Table 27-2
.