Microchip Technology DM240015 データシート
2012-2013 Microchip Technology Inc.
DS30009312B-page 251
PIC24FJ128GC010 FAMILY
17.2
Setting Baud Rate When
Operating as a Bus Master
Operating as a Bus Master
To compute the Baud Rate Generator reload value, use
.
EQUATION 17-1:
COMPUTING BAUD RATE
RELOAD VALUE
RELOAD VALUE
(
)
17.3
Slave Address Masking
The I2CxMSK register (
) designates
address bit positions as “don’t care” for both 7-Bit and
10-Bit Addressing modes. Setting a particular bit loca-
tion (= 1) in the I2CxMSK register causes the slave
module to respond, whether the corresponding
address bit value is a ‘0’ or a ‘1’. For example, when
I2CxMSK is set to ‘00100000’, the slave module will
detect both addresses, ‘0000000’ and ‘0100000’.
To enable address masking, the Intelligent Peripheral
Management Interface (IPMI) must be disabled by
clearing the IPMIEN bit (I2CxCON<11>).
10-Bit Addressing modes. Setting a particular bit loca-
tion (= 1) in the I2CxMSK register causes the slave
module to respond, whether the corresponding
address bit value is a ‘0’ or a ‘1’. For example, when
I2CxMSK is set to ‘00100000’, the slave module will
detect both addresses, ‘0000000’ and ‘0100000’.
To enable address masking, the Intelligent Peripheral
Management Interface (IPMI) must be disabled by
clearing the IPMIEN bit (I2CxCON<11>).
TABLE 17-2:
I
2
C™ RESERVED ADDRESSES
Note 1:
Based on F
CY
= F
OSC
/2; Doze mode
and PLL are disabled.
2:
These clock rate values are for guid-
ance only. The actual clock rate can
be affected by various system-level
parameters. The actual clock rate
should be measured in its intended
application.
ance only. The actual clock rate can
be affected by various system-level
parameters. The actual clock rate
should be measured in its intended
application.
FSCL =
F
CY
I2CxBRG + 1 +
F
CY
10,000,000
I2CxBRG =
F
CY
10,000,000
F
CY
FSCL
–
– 1
or:
(
)
Note:
As a result of changes in the I
2
C™ proto-
reserved and will not be Acknowledged in
Slave mode. This includes any address
mask settings that include any of these
addresses.
Slave mode. This includes any address
mask settings that include any of these
addresses.
TABLE 17-1:
I
2
C™ CLOCK RATES
)
Required System F
SCL
F
CY
I2CxBRG Value
Actual F
SCL
(Decimal)
(Hexadecimal)
100 kHz
16 MHz
157
9D
100 kHz
100 kHz
8 MHz
78
4E
100 kHz
100 kHz
4 MHz
39
27
99 kHz
400 kHz
16 MHz
37
25
404 kHz
400 kHz
8 MHz
18
12
404 kHz
400 kHz
4 MHz
9
9
385 kHz
400 kHz
2 MHz
4
4
385 kHz
1 MHz
16 MHz
13
D
1.026 MHz
1 MHz
8 MHz
6
6
1.026 MHz
1 MHz
4 MHz
3
3
0.909 MHz
Note 1:
Based on F
CY
= F
OSC
/2; Doze mode and PLL are disabled.
2:
These clock rate values are for guidance only. The actual clock rate can be affected by various
system-level parameters. The actual clock rate should be measured in its intended application.
system-level parameters. The actual clock rate should be measured in its intended application.
Slave Address
R/W Bit
Description
0000 000
0
General Call Address
)
0000 000
1
Start Byte
0000 001
x
CBus Address
0000 01x
x
Reserved
0000 1xx
x
HS Mode Master Code
1111 0xx
x
10-Bit Slave Upper Byte
)
1111 1xx
x
Reserved
Note 1:
The address bits listed here will never cause an address match, independent of address mask settings.
2:
The address will be Acknowledged only if GCEN = 1.
3:
A match on this address can only occur on the upper byte in 10-Bit Addressing mode.