Microchip Technology MA300015 データシート

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© 2011 Microchip Technology Inc.
DS70150E-page 119
dsPIC30F6010A/6015
18.0
UNIVERSAL ASYNCHRONOUS 
RECEIVER TRANSMITTER 
(UART) MODULE
This section describes the Universal Asynchronous
Receiver/Transmitter Communications module. 
18.1
UART Module Overview
The key features of the UART module are:
• Full-duplex, 8 or 9-bit data communication
• Even, Odd or No Parity options (for 8-bit data)
• One or two Stop bits
• Fully integrated Baud Rate Generator with 16-bit 
prescaler
• Baud rates range from 38 bps to 1.875 Mbps at a 
30 MHz instruction rate
• 4-word deep transmit data buffer
• 4-word deep receive data buffer
• Parity, Framing and Buffer Overrun error detection
• Support for Interrupt only on Address Detect 
(9th bit = 1)
• Separate Transmit and Receive Interrupts
• Loopback mode for diagnostic support
FIGURE 18-1:
UART TRANSMITTER BLOCK DIAGRAM
Note:
This data sheet summarizes features of
this group of dsPIC30F devices and is not
intended to be a complete reference
source. For more information on the CPU,
peripherals, register descriptions and
general device functionality, refer to the
dsPIC30F Family Reference Manual
(DS70046).
Write
Write
UTX8
UxTXREG Low Byte
Load TSR
Transmit Control
– Control TSR
– Control Buffer
– Generate Flags
– Generate Interrupt
Control and Status bits
UxTXIF
Data
‘0’ (Start)
‘1’ (Stop)
Parity
Parity
Generator
    Transmit Shift Register (UxTSR)
16 Divider
Control
Signals
16X Baud Clock
from Baud Rate
Generator
Internal Data Bus
UTXBRK 
Note: x = 1 or 2. 
UxTX