Microchip Technology MA330016 データシート
dsPIC33FJ32GP202/204 and dsPIC33FJ16GP304
DS70290J-page 156
© 2007-2011 Microchip Technology Inc.
15.1
SPI Helpful Tips
1.
In Frame mode, if there is a possibility that the
master may not be initialized before the slave:
a) If FRMPOL (SPIxCON2<13>) = 1, use a
master may not be initialized before the slave:
a) If FRMPOL (SPIxCON2<13>) = 1, use a
pull-down resistor on SSx.
b) If FRMPOL = 0, use a pull-up resistor on
SSx.
2.
In non-framed 3-wire mode, (i.e., not using SSx
from a master):
a) If CKP (SPIxCON1<6>) = 1, always place a
from a master):
a) If CKP (SPIxCON1<6>) = 1, always place a
pull-up resistor on SSx.
b) If CKP = 0, always place a pull-down
resistor on SSx.
3.
FRMEN (SPIxCON2<15>) = 1 and SSEN
(SPIxCON1<7>) = 1 are exclusive and invalid.
In Frame mode, SCKx is continuous and the
Frame sync pulse is active on the SSx pin,
which indicates the start of a data frame.
(SPIxCON1<7>) = 1 are exclusive and invalid.
In Frame mode, SCKx is continuous and the
Frame sync pulse is active on the SSx pin,
which indicates the start of a data frame.
4.
In Master mode only, set the SMP bit
(SPIxCON1<9>) to a ‘1’ for the fastest SPI data
rate possible. The SMP bit can only be set at the
same time or after the MSTEN bit
(SPIxCON1<5>) is set.
(SPIxCON1<9>) to a ‘1’ for the fastest SPI data
rate possible. The SMP bit can only be set at the
same time or after the MSTEN bit
(SPIxCON1<5>) is set.
5.
To avoid invalid slave read data to the master,
the user’s master software must guarantee
enough time for slave software to fill its write buf-
fer before the user application initiates a master
write/read cycle. It is always advisable to pre-
load the SPIxBUF transmit register in advance
of the next master transaction cycle. SPIxBUF is
transferred to the SPI shift register and is empty
once the data transmission begins.
the user’s master software must guarantee
enough time for slave software to fill its write buf-
fer before the user application initiates a master
write/read cycle. It is always advisable to pre-
load the SPIxBUF transmit register in advance
of the next master transaction cycle. SPIxBUF is
transferred to the SPI shift register and is empty
once the data transmission begins.
15.2
SPI Resources
Many useful resources are provided on the main prod-
uct page of the Microchip web site for the devices listed
in this data sheet. This product page, which can be
accessed using this
uct page of the Microchip web site for the devices listed
in this data sheet. This product page, which can be
accessed using this
, contains the latest updates
and additional information.
15.2.1
KEY RESOURCES
• Section 18. “Serial Peripheral Interface (SPI)”
(DS70206)
• Code Samples
• Application Notes
• Software Libraries
• Webinars
• All related dsPIC33F/PIC24H Family Reference
• Application Notes
• Software Libraries
• Webinars
• All related dsPIC33F/PIC24H Family Reference
Manuals Sections
• Development Tools
Note:
This insures that the first frame
transmission after initialization is not
shifted or corrupted.
transmission after initialization is not
shifted or corrupted.
Note:
This will insure that during power-up and
initialization the master/slave will not lose
sync due to an errant SCK transition that
would cause the slave to accumulate data
shift errors for both transmit and receive
appearing as corrupted data.
initialization the master/slave will not lose
sync due to an errant SCK transition that
would cause the slave to accumulate data
shift errors for both transmit and receive
appearing as corrupted data.
Note:
Not all third-party devices support Frame
mode timing. Refer to the SPI electrical
characteristics for details.
mode timing. Refer to the SPI electrical
characteristics for details.
Note:
In the event you are not able to access
the product page using the link above,
enter this URL in your browser:
the product page using the link above,
enter this URL in your browser: