Microchip Technology MCP1631RD-MCC2 データシート
2006-2012 Microchip Technology Inc.
DS41291G-page 199
PIC16F882/883/884/886/887
13.4.5
BAUD RATE GENERATOR
In I
2
C Master mode, the reload value for the BRG is
located in the lower 7 bits of the SSPADD register
(
(
). When the BRG is loaded with this
value, the BRG counts down to 0 and stops until
another reload has taken place. The BRG count is
decremented twice per instruction cycle (T
another reload has taken place. The BRG count is
decremented twice per instruction cycle (T
CY
) on the
Q2 and Q4 clocks. In I
2
C Master mode, the BRG is
reloaded automatically. If clock arbitration is taking
place, for instance, the BRG will be reloaded when the
SCL pin is sampled high (
place, for instance, the BRG will be reloaded when the
SCL pin is sampled high (
).
FIGURE 13-11:
BAUD RATE GENERATOR BLOCK DIAGRAM
FIGURE 13-12:
BAUD RATE GENERATOR TIMING WITH CLOCK ARBITRATION
SSPM<3:0>
BRG Down Counter
CLKOUT
F
OSC
/4
SSPADD<6:0>
SSPM<3:0>
SCL
Reload
Control
Control
Reload
SDA
SCL
SCL de-asserted but slave holds
DX-1
DX
BRG
SCL is sampled high, reload takes
place and BRG starts its count
place and BRG starts its count
03h
02h
01h
00h (hold off)
03h
02h
Reload
BRG
Value
Value
SCL low (clock arbitration)
SCL allowed to transition high
BRG decrements on
Q2 and Q4 cycles