Microchip Technology MA160014 データシート

 2010-2012 Microchip Technology Inc.

DS41412F-page 163

The Timer1/3/5 module is a 16-bit timer/counter with
the following features:

• 16-bit timer/counter register pair (TMRxH:TMRxL)

• Programmable internal or external clock source

• 2-bit prescaler

• Dedicated Secondary 32 kHz oscillator circuit

• Optionally synchronized comparator out

• Multiple Timer1/3/5 gate (count enable) sources

• Interrupt on overflow

• Wake-up on overflow (external clock, 

Asynchronous mode only)

• 16-Bit Read/Write Operation

• Time base for the Capture/Compare function

• Special Event Trigger (with CCP/ECCP)

• Selectable Gate Source Polarity

• Gate Toggle mode

• Gate Single-pulse mode

• Gate Value Status

• Gate Event Interrupt

 is a block diagram of the Timer1/3/5

module.

TMRxH

TMRxL

TxSYNC

TxCKPS<1:0>

Prescaler

1, 2, 4, 8

0

1

Synchronized

clock input

2

Set flag bit
TMRxIF on
Overflow

TMRx

TMRxON

ST Buffer is high speed type when using TxCKI.

Timer1/3/5 register increments on rising edge.

Synchronize does not operate while in Sleep.

See 

 for 16-Bit Read/Write Mode Block Diagram.

T1CKI is not available when the secondary oscillator is enabled. (SOSCGO = 1 or TXSOSCEN = 1)

T3CKI is not available when the secondary oscillator is enabled, unless T3CMX = 1.

Synchronized comparator output should not be used in conjunction with synchronized TxCKI.

TxG

F

OSC

/4

Internal

Clock

SOSCOUT

1

0

TxCKI

TMRxCS<1:0>

Synchronize

det

Sleep input

TMRxGE

0

1

00

01

10

11

TxGPOL

D

Q

CK

Q

0

1

TxGVAL

TxGTM

Single Pulse

Acq. Control

TxGSPM

TxGGO/DONE

TxGSS<1:0>

10

11

00

01

F

OSC

Internal

Clock

Reserved

R

D

EN

Q

Q1

RD

TXGCON

Data Bus

det

Interrupt

TMRxGIF

Set

TxCLK

F

OSC

/2

Internal

Clock

D

EN

Q

TxG_IN

TMRxON

Timer2/4/6 Match 

PR2/4/6

sync_C2OUT

sync_C1OUT

To Comparator Module

TxSOSCEN

Secondary
Oscillator
Module
See Figure 2-4

TxCLK_EXT_SRC