Microchip Technology MA160014 データシート
PIC18(L)F2X/4XK22
DS41412F-page 262
2010-2012 Microchip Technology Inc.
REGISTER 15-3:
SSPxCON2: SSPx CONTROL REGISTER 2
R/W-0
R-0
R/W-0
R/S/HC-0
R/S/HC-0
R/S/HC-0
R/S/HC-0
R/W/HC-0
GCEN
ACKSTAT
ACKDT
ACKEN
(1)
RCEN
(1)
PEN
(1)
RSEN
(1)
SEN
(1)
bit 7
bit 0
Legend:
R = Readable bit
W = Writable bit
U = Unimplemented bit, read as ‘0’
u = Bit is unchanged
x = Bit is unknown
-n/n = Value at POR and BOR/Value at all other Resets
‘1’ = Bit is set
‘0’ = Bit is cleared
HC = Cleared by hardware
S = User set
bit 7
GCEN: General Call Enable bit (in I
2
C Slave mode only)
1
= Enable interrupt when a general call address (0x00 or 00h) is received in the SSPxSR
0
= General call address disabled
bit 6
ACKSTAT: Acknowledge Status bit (in I
2
C mode only)
1
= Acknowledge was not received
0
= Acknowledge was received
bit 5
ACKDT: Acknowledge Data bit (in I
2
C mode only)
In Receive mode:
Value transmitted when the user initiates an Acknowledge sequence at the end of a receive
1
Value transmitted when the user initiates an Acknowledge sequence at the end of a receive
1
= Not Acknowledge
0
= Acknowledge
bit 4
ACKEN
(1)
: Acknowledge Sequence Enable bit (in I
2
C Master mode only)
In Master Receive mode:
1
= Initiate Acknowledge sequence on SDAx and SCLx pins, and transmit ACKDT data bit.
Automatically cleared by hardware.
0
= Acknowledge sequence idle
bit 3
RCEN
(1)
: Receive Enable bit (in I
2
C Master mode only)
1
= Enables Receive mode for I
2
C
0
= Receive idle
bit 2
PEN
(1)
: Stop Condition Enable bit (in I
2
C Master mode only)
SCKx Release Control:
1
= Initiate Stop condition on SDAx and SCLx pins. Automatically cleared by hardware.
0
= Stop condition Idle
bit 1
RSEN
(1)
: Repeated Start Condition Enabled bit (in I
2
C Master mode only)
1
= Initiate Repeated Start condition on SDAx and SCLx pins. Automatically cleared by hardware.
0
= Repeated Start condition Idle
bit 0
SEN
(1)
: Start Condition Enabled bit (in I
2
C Master mode only)
In Master mode:
1
1
= Initiate Start condition on SDAx and SCLx pins. Automatically cleared by hardware.
0
= Start condition Idle
In Slave mode:
1
1
= Clock stretching is enabled for both slave transmit and slave receive (stretch enabled)
0
= Clock stretching is disabled
Note 1:
For bits ACKEN, RCEN, PEN, RSEN, SEN: If the I
2
C module is not in the Idle mode, this bit may not be
set (no spooling) and the SSPxBUF may not be written (or writes to the SSPxBUF are disabled).