Microchip Technology MA160014 データシート
PIC18(L)F2X/4XK22
DS41412F-page 270
2010-2012 Microchip Technology Inc.
16.1.1.5
TSR Status
The TRMT bit of the TXSTAx register indicates the
status of the TSR register. This is a read-only bit. The
TRMT bit is set when the TSR register is empty and is
cleared when a character is transferred to the TSR
register from the TXREGx. The TRMT bit remains clear
until all bits have been shifted out of the TSR register.
No interrupt logic is tied to this bit, so the user needs to
poll this bit to determine the TSR status.
status of the TSR register. This is a read-only bit. The
TRMT bit is set when the TSR register is empty and is
cleared when a character is transferred to the TSR
register from the TXREGx. The TRMT bit remains clear
until all bits have been shifted out of the TSR register.
No interrupt logic is tied to this bit, so the user needs to
poll this bit to determine the TSR status.
16.1.1.6
Transmitting 9-Bit Characters
The EUSART supports 9-bit character transmissions.
When the TX9 bit of the TXSTAx register is set the
EUSART will shift nine bits out for each character trans-
mitted. The TX9D bit of the TXSTAx register is the
ninth, and Most Significant, data bit. When transmitting
9-bit data, the TX9D data bit must be written before
writing the eight Least Significant bits into the TXREGx.
All nine bits of data will be transferred to the TSR shift
register immediately after the TXREGx is written.
When the TX9 bit of the TXSTAx register is set the
EUSART will shift nine bits out for each character trans-
mitted. The TX9D bit of the TXSTAx register is the
ninth, and Most Significant, data bit. When transmitting
9-bit data, the TX9D data bit must be written before
writing the eight Least Significant bits into the TXREGx.
All nine bits of data will be transferred to the TSR shift
register immediately after the TXREGx is written.
A special 9-bit Address mode is available for use with
multiple receivers. See
multiple receivers. See
for more information on the Address mode.
16.1.1.7
Asynchronous Transmission Setup:
1.
Initialize the SPBRGHx:SPBRGx register pair
and the BRGH and BRG16 bits to achieve the
desired baud rate (see
and the BRGH and BRG16 bits to achieve the
desired baud rate (see
2.
Set the RXx/DTx and TXx/CKx TRIS controls to
‘1’.
‘1’.
3.
Enable the asynchronous serial port by clearing
the SYNC bit and setting the SPEN bit.
the SYNC bit and setting the SPEN bit.
4.
If 9-bit transmission is desired, set the TX9 con-
trol bit. A set ninth data bit will indicate that the
eight Least Significant data bits are an address
when the receiver is set for address detection.
trol bit. A set ninth data bit will indicate that the
eight Least Significant data bits are an address
when the receiver is set for address detection.
5.
Set the CKTXP control bit if inverted transmit
data polarity is desired.
data polarity is desired.
6.
Enable the transmission by setting the TXEN
control bit. This will cause the TXxIF interrupt bit
to be set.
control bit. This will cause the TXxIF interrupt bit
to be set.
7.
If interrupts are desired, set the TXxIE interrupt
enable bit. An interrupt will occur immediately
provided that the GIE/GIEH and PEIE/GIEL bits
of the INTCON register are also set.
enable bit. An interrupt will occur immediately
provided that the GIE/GIEH and PEIE/GIEL bits
of the INTCON register are also set.
8.
If 9-bit transmission is selected, the ninth bit
should be loaded into the TX9D data bit.
should be loaded into the TX9D data bit.
9.
Load 8-bit data into the TXREGx register. This
will start the transmission.
will start the transmission.
FIGURE 16-3:
ASYNCHRONOUS TRANSMISSION
Note:
The TSR register is not mapped in data
memory, so it is not available to the user.
memory, so it is not available to the user.
Word 1
Stop bit
Word 1
Transmit Shift Reg
Transmit Shift Reg
Start bit
bit 0
bit 1
bit 7/8
Write to TXREGx
Word 1
BRG Output
(Shift Clock)
(Shift Clock)
TXx/CKx
TXxIF bit
(Transmit Buffer
Reg. Empty Flag)
TRMT bit
(Transmit Shift
Reg. Empty Flag)
1 T
CY
pin