Microchip Technology MA160014 データシート
2010-2012 Microchip Technology Inc.
DS41412E-page 37
PIC18(L)F2X/4XK22
2.6.1.1
OSCTUNE Register
The HFINTOSC/MFINTOSC oscillator circuits are
factory calibrated but can be adjusted in software by
writing to the TUN<5:0> bits of the OSCTUNE register
(
factory calibrated but can be adjusted in software by
writing to the TUN<5:0> bits of the OSCTUNE register
(
The default value of the TUN<5:0> is ‘000000’. The
value is a 6-bit two’s complement number.
value is a 6-bit two’s complement number.
When the OSCTUNE register is modified, the
HFINTOSC/MFINTOSC frequency will begin shifting to
the new frequency. Code execution continues during this
shift. There is no indication that the shift has occurred.
HFINTOSC/MFINTOSC frequency will begin shifting to
the new frequency. Code execution continues during this
shift. There is no indication that the shift has occurred.
The TUN<5:0> bits in OSCTUNE do not affect the
LFINTOSC frequency. Operation of features that
depend on the LFINTOSC clock source frequency, such
as the Power-up Timer (PWRT), Watchdog Timer
(WDT), Fail-Safe Clock Monitor (FSCM) and
peripherals, are not affected by the change in frequency.
LFINTOSC frequency. Operation of features that
depend on the LFINTOSC clock source frequency, such
as the Power-up Timer (PWRT), Watchdog Timer
(WDT), Fail-Safe Clock Monitor (FSCM) and
peripherals, are not affected by the change in frequency.
The OSCTUNE register also implements the INTSRC
and PLLEN bits, which control certain features of the
internal oscillator block.
and PLLEN bits, which control certain features of the
internal oscillator block.
The INTSRC bit allows users to select which internal
oscillator provides the clock source when the
31.25 kHz frequency option is selected. This is covered
in greater detail in
oscillator provides the clock source when the
31.25 kHz frequency option is selected. This is covered
in greater detail in
.
The PLLEN bit controls the operation of the frequency
multiplier, PLL, for all primary external clock sources
and internal oscillator modes. However, the PLL is
intended for operation with clock sources between
4 MHz and 16 MHz. For more details about the function
of the PLLEN bit, see
multiplier, PLL, for all primary external clock sources
and internal oscillator modes. However, the PLL is
intended for operation with clock sources between
4 MHz and 16 MHz. For more details about the function
of the PLLEN bit, see
2.7
Register Definitions: Oscillator Tuning
REGISTER 2-3:
OSCTUNE: OSCILLATOR TUNING REGISTER
R/W-0 R/W-0
R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0
INTSRC
PLLEN
TUN<5:0>
bit 7
bit 0
Legend:
R = Readable bit
W = Writable bit
U = Unimplemented bit, read as ‘0’
-n = Value at POR
‘1’ = Bit is set
‘0’ = Bit is cleared
x = Bit is unknown
bit 7
INTSRC: Internal Oscillator Low-Frequency Source Select bit
1
= 31.25 kHz device clock derived from the MFINTOSC or HFINTOSC source
0
= 31.25 kHz device clock derived directly from LFINTOSC internal oscillator
bit 6
PLLEN: Frequency Multiplier 4xPLL for HFINTOSC Enable bit
1
= PLL enabled
0
= PLL disabled
bit 5-0
TUN<5:0>: Frequency Tuning bits – use to adjust MFINTOSC and HFINTOSC frequencies
011111
= Maximum frequency
011110
=
• • •
000001
000001
=
000000
= Oscillator module (HFINTOSC and MFINTOSC) are running at the factory calibrated
frequency.
111111
=
• • •
100000
100000
= Minimum frequency
Note 1:
The PLLEN bit is active for all the primary clock sources (internal or external) and is designed to operate
with clock frequencies between 4 MHz and 16 MHz.
with clock frequencies between 4 MHz and 16 MHz.