Microchip Technology DV320032 データシート
2012-2013 Microchip Technology Inc.
DS60001185C-page 179
PIC32MX330/350/370/430/450/470
13.0 TIMER1
This family of PIC32 devices features one synchronous/
asynchronous 16-bit timer that can operate as a free-
running interval timer for various timing applications and
counting external events. This timer can also be used
with the Low-Power Secondary Oscillator (S
asynchronous 16-bit timer that can operate as a free-
running interval timer for various timing applications and
counting external events. This timer can also be used
with the Low-Power Secondary Oscillator (S
OSC
) for
Real-Time Clock (RTC) applications. The following
modes are supported:
• Synchronous Internal Timer
• Synchronous Internal Gated Timer
• Synchronous External Timer
• Asynchronous External Timer
modes are supported:
• Synchronous Internal Timer
• Synchronous Internal Gated Timer
• Synchronous External Timer
• Asynchronous External Timer
13.1
Additional Supported Features
• Selectable clock prescaler
• Timer operation during CPU Idle and Sleep mode
• Fast bit manipulation using CLR, SET and INV
• Timer operation during CPU Idle and Sleep mode
• Fast bit manipulation using CLR, SET and INV
registers
• Asynchronous mode can be used with the S
OSC
to function as a Real-Time Clock (RTC)
FIGURE 13-1:
TIMER1 BLOCK DIAGRAM
Note 1: This data sheet summarizes the features
of the PIC32MX330/350/370/430/450/
470 family of devices. It is not intended to
be a comprehensive reference source.
To complement the information in this
data sheet, refer to Section 14. “Timers”
(DS60001105) in the “PIC32 Family
Reference Manual”, which is available
from the Microchip web site
(
470 family of devices. It is not intended to
be a comprehensive reference source.
To complement the information in this
data sheet, refer to Section 14. “Timers”
(DS60001105) in the “PIC32 Family
Reference Manual”, which is available
from the Microchip web site
(
2: Some registers and associated bits
described in this section may not be
available on all devices. Refer to
available on all devices. Refer to
in
this data sheet for device-specific register
and bit information.
and bit information.
ON
Sync
SOSCI
SOSCO/T1CK
TMR1
T1IF
Equal
16-bit Comparator
PR1
Reset
SOSCEN
Event Flag
1
0
TSYNC
TGATE
TGATE
PBCLK
1
0
TCS
Gate
Sync
TCKPS<1:0>
Prescaler
2
1, 8, 64, 256
x 1
1 0
0 0
Q
Q
D
Note:
The default state of the SOSCEN (OSCCON<1>) bit during a device Reset is controlled by the FSOSCEN
bit in Configuration Word, DEVCFG1.
bit in Configuration Word, DEVCFG1.
Data Bus<31:0>
<15:0>