Freescale Semiconductor Enhanced serial module TWR-SER2 TWR-SER2 TWR-SER2 ユーザーズマニュアル
製品コード
TWR-SER2
TWR-SER2 User’s Manual
Page 10 of 17
If needed the CAN transceiver signals can be isolated from the Tower Elevator using J4.
Pins
Description
1-2
Remove to Isolate CAN_S
3-4
Remove to Isolate CAN_TX
5-6
Remove to Isolate CAN_RX
3.7 Elevator Connections
The TWR-SER2 features two expansion card-edge connectors that interface to Elevator boards in a
Tower System: the Primary and Secondary Elevator connectors. Table 2 provides the pinout for the
Primary and Secondary Elevator Connector. An “X” in the “Used” column indicated that there is a
connection from the TWR-MEM to that pin on the Elevator connector. An “X” in the “Jmp” column
indicates that a jumper is available that can configure or isolate the connection from the Elevator
connector.
Tower System: the Primary and Secondary Elevator connectors. Table 2 provides the pinout for the
Primary and Secondary Elevator Connector. An “X” in the “Used” column indicated that there is a
connection from the TWR-MEM to that pin on the Elevator connector. An “X” in the “Jmp” column
indicates that a jumper is available that can configure or isolate the connection from the Elevator
connector.
Table 2 - TWR-SER2 Primary Elevator Connector Pinout
TWR-SER2 Primary Connector
Pin
Name
Usage
Used Jmp
Pin
Name
Usage
Used Jmp
B1
5V
5.0V Power
X
A1
5V
5.0V Power
X
B2
GND
Ground
X
A2
GND
Ground
X
B3
3.3V
3.3V Power
X
A3
3.3V
3.3V Power
X
B4
ELE_PS_SENSE
Elevator Power Sense
X
A4
3.3V
3.3V Power
X
B5
GND
Ground
X
A5
GND
Ground
X
B6
GND
Ground
X
A6
GND
Ground
X
B7
SDHC_CLK / SPI1_CLK
A7
I2C0_SCL
B8
SDHC_D3 / SPI1_CS1_b
A8
I2C0_SDA
B9
SDHC_D3 / SPI1_CS0_b
A9
GPIO9 / UART1_CTS
B10
SDHC_CMD / SPI1_MOSI
A10
GPIO8 / SDHC_D2
B11
SDHC_D0 / SPI1_MISO
A11
GPIO7 / SD_WP_DET
B12
ETH_COL
MII_COL
X
A12
ETH_CRS
MII_CRS
X
B13
ETH_RXER
MII_RXER / RMII0_RXER
X
A13
ETH_MDC
MII_MDC /
RMII0_MDC
X
B14
ETH_TXCLK
MII_TXCLK
X
A14
ETH_MDIO
MII_MDIO /
RMII0_MDIO
X
B15
ETH_TXEN
MII_TXEN / RMII0_TXEN
X
A15
ETH_RXCLK
MII_RXCLK
X
B16
ETH_TXER
A16
ETH_RXDV
MII_RXDV /
RMII0_CRS_DV
X
B17
ETH_TXD3
MII_TXD3
X
A17
ETH_RXD3
MII_RXD3
X
B18
ETH_TXD2
MII_TXD2
X
A18
ETH_RXD2
MII_RXD2
X
B19
ETH_TXD1
MII_TXD1 / RMII0_TXD1
X
A19
ETH_RXD1
MII_RXD1 /
RMII0_RXD1
X
B20
ETH_TXD0
MII_TXD0 / RMII0_TXD0
X
A20
ETH_RXD0
MII_RXD0 /
RMII0_RXD0
X
B21
GPIO1 /UART1_RTS
X
A21
I2S0_MCLK