Freescale Semiconductor Evaluation Kit (EVK) for the i.MX51 Applications Processor MCIMX51EXP MCIMX51EXP データシート
製品コード
MCIMX51EXP
Electrical Characteristics
i.MX51 Applications Processors for Consumer and Industrial Products, Rev. 6
Freescale Semiconductor
69
4.6.9
DDR2 SDRAM Specific Parameters
shows the timing parameters for DDR2. The timing parameters for this diagram appear in
.
Figure 35. DDR2 SDRAM Basic Timing Parameters
Table 58. DDR2 SDRAM Timing Parameter Table
ID
Parameter
Symbol
SDCLK = 200 MHz
Unit
Min
Max
DDR1
SDRAM clock high-level width
t
CH
0.45
0.55
t
CK
DDR2
SDRAM clock low-level width
t
CL
0.45
0.55
t
CK
DDR3
SDRAM clock cycle time
t
CK
5
—
ns
DDR4
CS, RAS, CAS, CKE, WE, ODT setup time
t
IS
1
1.5
—
ns
DDR5
CS, RAS, CAS, CKE, WE, ODT hold time
t
1.7
—
ns
SDCLK
WE
ADDR
ROW/BA
COL/BA
CS
CAS
RAS
DDR1
DDR3
DDR2
DDR4
DDR4
DDR4
DDR5
DDR5
DDR5
DDR5
DDR6
DDR7
SDCLK
ODT/CKE
DDR4