Analog Devices AD9736 Evaluation Board AD9736-DPG2-EBZ AD9736-DPG2-EBZ データシート

製品コード
AD9736-DPG2-EBZ
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10-/12-/14-Bit, 1200 MSPS DACS
 
AD9734/AD9735/AD9736
 
 
Rev. A 
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Tel: 781.329.4700 
www.analog.com
 
Fax: 781.461.3113 
©2006 Analog Devices, Inc. All rights reserved. 
FEATURES 
Pin-compatible family 
Excellent dynamic performance 
AD9736: SFDR = 82 dBc at f
OUT
 = 30 MHz 
AD9736: SFDR = 69 dBc at f
OUT
 = 130 MHz 
AD9736: IMD = 87 dBc at f
OUT
 = 30 MHz  
AD9736: IMD = 82 dBc at f
OUT
 = 130 MHz  
LVDS data interface with on-chip 100 Ω terminations 
Built-in self test 
LVDS sampling integrity 
LVDS-to-DAC data transfer integrity 
Low power: 380 mW (I
FS
 = 20 mA; f
OUT
 = 330 MHz) 
1.8/3.3 V dual-supply operation 
Adjustable analog output 
8.66 mA to 31.66 mA (R
L
 = 25 Ω to 50 Ω)  
On-chip 1.2 V reference  
160-lead chip scale ball grid array (CSP_BGA) package 
APPLICATIONS 
Broadband communications systems  
Cellular infrastructure (digital predistortion) 
Point-to-point wireless  
CMTS/VOD 
Instrumentation, automatic test equipment  
Radar, avionics  
GENERAL DESCRIPTION 
The AD9736, AD9735, and AD9734 are high performance, high 
frequency DACs that provide sample rates of up to 1200 MSPS, 
permitting multicarrier generation up to their Nyquist 
frequency. The AD9736 is the 14-bit member of the family, 
while the AD9735 and the AD9734 are the 12-bit and 10-bit 
members, respectively. They include a serial peripheral interface 
(SPI) port that provides for programming of many internal 
parameters and enables readback of status registers.  
A reduced-specification LVDS interface is utilized to achieve 
the high sample rate. The output current can be programmed 
over a range of 8.66 mA to 31.66 mA. The AD973x family is 
manufactured on a 0.18 μm CMOS process and operates from 
1.8 V and 3.3 V supplies for a total power consumption of 
380 mW in bypass mode. It is supplied in a 160-lead chip scale 
ball grid array for reduced package parasitics. 
FUNCTIONAL BLOCK DIAGRAM 
LVDS
RE
CE
IV
E
R
S
Y
NCHRONIZE
R
BAND GAP
DATACLK_IN+
DATACLK_IN–
DB[13:0]–
DB[13:0]+
SPI
14-, 12-,
10-BIT DAC
CORE
IOUTA
IOUTB
SDO
SDIO
SCLK
CSB
LVDS
DRIV
E
R
CONTROLLER
REFERENCE
CURRENT
DACCLK–
IRQ
DACCLK+
I120
VREF
RESET
DATACLK_OUT+
DATACLK_OUT–
S1 S2 S3
C1
C2
C3
C2
C1S1
S3
S2
C3
04862-001
CLOCK
DISTRIBUTION
 
Figure 1. 
PRODUCT HIGHLIGHTS  
1.  Low noise and intermodulation distortion (IMD) features 
enable high quality synthesis of wideband signals at inter-
mediate frequencies up to 600 MHz.  
2.  Double data rate (DDR) LVDS data receivers support the 
maximum conversion rate of 1200 MSPS.  
3.  Direct pin programmability of basic functions or SPI port 
access offers complete control of all AD973x family 
functions.  
4.  Manufactured on a CMOS process, the AD973x family 
uses a proprietary switching technique that enhances 
dynamic performance.  
5.  The current output(s) of the AD9736 family are easily con-
figured for single-ended or differential circuit topologies.