Analog Devices Blackfin® A-V EZ-Extender® ADZS-BFAV-EZEXT ADZS-BFAV-EZEXT データシート

Blackfin A-V EZ-Extender Manual

2-13 

When the 

JP7.1/2

 jumper is installed, the SPORT signals are routed for 

I

2

S SPORT communication protocol mode. To accomplish this, the 

receive and transmit clocks of the processor are driven by the output clock 
of the AD1836A. The same is done for the frame sync signals. 

The 

JP7.3/4

 and 

JP7.5/6

 jumpers connect data output pins (

ASDATA1

 and 

ASDATA2

) of the audio codec to the primary and secondary SPORT data 

input pins of the processor. The audio codec is driving these pins—with 
the help of the 

JP7.3/4

 and 

JP7.5/6

 jumpers, the processor’s pins can be 

reused when the audio codec is disabled.

The source of the PPI frame sync signals depends on the PPI port driving 
the 

VID_OUT

 bus. When using 

PPI0

, place the jumpers at 

JP8.1/3

 and 

JP8.2/4

. When using 

PPI1

, place the jumpers at 

JP8.3/5

 and 

JP8.4/6

. 

To enable the 

VID_OUT

 frame sync signals, install the 

JP8.7/8

 jumper. 

Table 2-8. Setting Direction of PPI0_SYNC2 (JP6.2/4/6)

JP6.2/4

Controlled by flag pin 

JP6.4/6

Input to processor

Uninstalled Output 

from 

processor