Analog Devices AD8260 Evaluation Board AD8260-EVALZ AD8260-EVALZ データシート
製品コード
AD8260-EVALZ
AD8260
Rev. A | Page 22 of 32
PRECAUTIONS TO BE OBSERVED DURING HALF-
DUPLEX OPERATION
During receive, when the high current driver-amplifier is
disabled, its gain setting resistors provide a signal path from
input to output. To prevent inadvertent DAC signals from being
transmitted while receiving via the preamplifier and DGA, the
DAC in Figure 64 must have no output signal.
During transmit, the preamplifier and VGA should be disabled
through any of the nongain-setting codes (see Table 4).
disabled, its gain setting resistors provide a signal path from
input to output. To prevent inadvertent DAC signals from being
transmitted while receiving via the preamplifier and DGA, the
DAC in Figure 64 must have no output signal.
During transmit, the preamplifier and VGA should be disabled
through any of the nongain-setting codes (see Table 4).
VMID BUFFER
The VMID buffer is a dc bias source that generates the voltage
on Pin 1 and Pin 19, VMDO. Node VMDO cannot accommodate
large dynamic currents and requires excellent ac decoupling to
ground. A high quality 0.1μF capacitor located as close as
possible to Pin 1 and Pin 19 (see Figure 64) is normally sufficient
to decouple the high values of current from Node VMDO.
When operating with dual power supplies, the buffer is disabled
by connecting Pin VMDI, Pin VOCM, and Pin VMDO to ground.
Because the logic decoder in the DGA (GNSx inputs) requires
3.3 V of headroom, the positive supply rails must be 3.3 V or
greater whether single-ended or dual. If a dual supply is used,
the negative rails are the same magnitude (opposite polarity)
as the positive, that is, −3.3 V when VPOS, VPSB, and VPSR
are +3.3 V.
on Pin 1 and Pin 19, VMDO. Node VMDO cannot accommodate
large dynamic currents and requires excellent ac decoupling to
ground. A high quality 0.1μF capacitor located as close as
possible to Pin 1 and Pin 19 (see Figure 64) is normally sufficient
to decouple the high values of current from Node VMDO.
When operating with dual power supplies, the buffer is disabled
by connecting Pin VMDI, Pin VOCM, and Pin VMDO to ground.
Because the logic decoder in the DGA (GNSx inputs) requires
3.3 V of headroom, the positive supply rails must be 3.3 V or
greater whether single-ended or dual. If a dual supply is used,
the negative rails are the same magnitude (opposite polarity)
as the positive, that is, −3.3 V when VPOS, VPSB, and VPSR
are +3.3 V.
PREAMPLIFIER
The AD8260 includes an uncommitted current feedback op
amp to buffer the resistive attenuator of the DGA. External
resistors are used to adjust the gain. The preamplifier is
characterized with a noninverting gain of 6 dB (2×) and both
gain resistor values of 100 Ω. The preamplifier gain can be
increased using different gain ratios of R
amp to buffer the resistive attenuator of the DGA. External
resistors are used to adjust the gain. The preamplifier is
characterized with a noninverting gain of 6 dB (2×) and both
gain resistor values of 100 Ω. The preamplifier gain can be
increased using different gain ratios of R
FB1
and R
FB2
, trading off
bandwidth and offset voltage. The sum of the values of R
FB1
and
R
FB2
should be ≥200 Ω to maintain low distortion. R
FB2
should
be ≥100 Ω because it and an internal compensation capacitor
determine the −3 dB bandwidth of the amplifier. Smaller
resistor values may compromise preamplifier stability.
Because the AD8260 is internally dc-coupled, larger preamplifier
gains increase its offset voltage. The circuit contains an internal
bias resistor and some offset compensation; however, if a lower
value of offset voltage is required, it can be compensated by
connecting a resistor between the FDBK pin and the supply
voltage. If the offset is negative, the resistor value connects to
the negative supply; otherwise, it connects to the positive supply.
For larger gains, the overall noise is reduced if a low value of
R
resistor values may compromise preamplifier stability.
Because the AD8260 is internally dc-coupled, larger preamplifier
gains increase its offset voltage. The circuit contains an internal
bias resistor and some offset compensation; however, if a lower
value of offset voltage is required, it can be compensated by
connecting a resistor between the FDBK pin and the supply
voltage. If the offset is negative, the resistor value connects to
the negative supply; otherwise, it connects to the positive supply.
For larger gains, the overall noise is reduced if a low value of
R
FB1
is selected. For values of R
FB1
= 20 Ω and R
FB2
= 301 Ω, the
preamplifier gain is 16× (24.1 dB) and the input-referred noise
is about 1.5 nV/√Hz. For this value of gain, the overall gain range
increases by 18 dB so that the absolute gain range is 12 dB to 42 dB.
is about 1.5 nV/√Hz. For this value of gain, the overall gain range
increases by 18 dB so that the absolute gain range is 12 dB to 42 dB.
PREAMPLIFIER NOISE
The total input-referred voltage and current noise of the positive
input of the preamplifier is about 2.4 nV/√Hz and 5 pA/√Hz,
respectively. The DGA output referred noise is about 25 nV/√Hz
at low gains and 39 nV/√Hz at the highest gain. The 25 nV/√Hz
divided by the DGA fixed gain of 8× results in 3.12 nV/√Hz
referred to the DGA input. Note that this value includes the
noise of the DGA gain setting resistors as well. If this voltage is
divided by the preamplifier gain of 2×, the DGA noise referred
all the way to the preamplifier input is about 1.56 nV/√Hz. From
this, it can be determined that the preamplifier, including the
100 Ω gain setting resistors, contributes about 1.8 nV/√Hz. The
two 100 Ω resistors each contribute 1.29 nV/√Hz at the output
of the preamplifier and 0.9 nV/√Hz referred to the input. With
the gain resistor noise subtracted, the preamplifier noise alone
is about 1.6 nV/√Hz.
Equation 1 shows the calculation that determines the output-
referred noise at maximum gain (24 dB or 16×).
input of the preamplifier is about 2.4 nV/√Hz and 5 pA/√Hz,
respectively. The DGA output referred noise is about 25 nV/√Hz
at low gains and 39 nV/√Hz at the highest gain. The 25 nV/√Hz
divided by the DGA fixed gain of 8× results in 3.12 nV/√Hz
referred to the DGA input. Note that this value includes the
noise of the DGA gain setting resistors as well. If this voltage is
divided by the preamplifier gain of 2×, the DGA noise referred
all the way to the preamplifier input is about 1.56 nV/√Hz. From
this, it can be determined that the preamplifier, including the
100 Ω gain setting resistors, contributes about 1.8 nV/√Hz. The
two 100 Ω resistors each contribute 1.29 nV/√Hz at the output
of the preamplifier and 0.9 nV/√Hz referred to the input. With
the gain resistor noise subtracted, the preamplifier noise alone
is about 1.6 nV/√Hz.
Equation 1 shows the calculation that determines the output-
referred noise at maximum gain (24 dB or 16×).
(
)
2
,
2
,
2
1
2
,
2
,
2
,
2
,
)
(
)
(
)
(
)
(
)
(
VGA
VGA
n
VGA
RFB2
n
VGA
FB
FB
RFB1
n
S
PrA
n
t
PrA
n
t
RS
n
out
n
A
e
A
e
A
R
R
e
R
i
A
e
A
e
e
×
+
×
+
×
×
+
×
+
×
+
×
=
−
(1)
where:
A
t
is the total gain from preamplifier input to the VGA output.
e
n
,
RS
is the noise of the source resistance.
e
n,PrA
is the input-referred voltage noise of the preamplifier.
i
n,PrA
is the current noise of the preamplifier at the PRAI pin.
R
S
is the source resistance.
A
VGA
is the VGA gain.
e
n,RFB1
is the voltage noise of R
FB1
.
e
n,RFB2
is the voltage noise of R
FB2
.
e
n,VGA
is the input-referred voltage noise of DGA (low gain output-referred noise divided by a fixed gain of 8×).