Analog Devices ADP5037CP Evaluation Board ADP5037CP-EVALZ ADP5037CP-EVALZ データシート

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ADP5037CP-EVALZ
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Dual 3 MHz, 800 mA Buck 
Regulators with Two 300 mA LDOs
Data Sheet 
 
 
Rev. D
 
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One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: 781.329.4700 
©2011–2013 Analog Devices, Inc. All rights reserved. 
FEATURES 
Main input voltage range: 2.3 V to 5.5 V 
Two 800 mA buck regulators and two 300 mA LDOs 
24-lead, 4 mm × 4 mm LFCSP package 
Regulator accuracy: ±1.8% 
Factory programmable or external adjustable VOUTx 
3 MHz buck operation with forced PWM and auto PWM/PSM 
modes 
BUCK1/BUCK2: output voltage range from 0.8 V to 3.8 V 
LDO1/LDO2: output voltage range from 0.8 V to 5.2 V 
LDO1/LDO2: input supply voltage from 1.7 V to 5.5 V 
LDO1/LDO2: high PSRR and low output noise 
APPLICATIONS 
Power for processors, ASICS, FPGAs, and RF chipsets 
Portable instrumentation and medical devices 
Space constrained devices 
GENERAL DESCRIPTION 
 combines two high performance buck regulators 
and two low dropout (LDO) regulators in a small, 24-lead 4 mm × 
4 mm LFCSP to meet demanding performance and board space 
requirements. 
The high switching frequency of the buck regulators enables tiny 
multilayer external components and minimizes the board space. 
When the MODE pin is set high, the buck regulators operate in 
forced PWM mode. When the MODE pin is set low and the 
load is above a predefined threshold, the buck regulators 
operate in PWM mode. When the load current falls below a 
predefined threshold, the regulator operates in power save 
mode (PSM), improving the light-load efficiency. 
Table 1. Family Models 
Model Channels 
Maximum 
Current Package 
2 Buck, 1 LDO 
800 mA, 
300 mA 
LFCSP (CP-24-10) 
2 Buck, 1 LDO 
1.2 A, 
300 mA 
LFCSP (CP-24-10) 
2 Buck, 2 LDOs 
1.2 A, 
300 mA 
LFCSP (CP-24-10), 
TSSOP (RE-28-1) 
2 Buck, 2 LDOs 
800 mA, 
300 mA 
LFCSP (CP-24-10) 
2 Buck, 2 LDOs with 
2 EN pins 
800 mA, 
300 mA 
WLCSP (CB-16-8) 
The two bucks operate out of phase to reduce the input capaci-
tor requirement. The low quiescent current, low dropout voltage, 
and wide input voltage range of th
 LDOs extend the 
battery life of portable devices. The 
 LDOs maintain 
power supply rejection greater than 60 dB for frequencies as 
high as 10 kHz while operating with a low headroom voltage.  
Regulators in th
 are activated though dedicated 
enable pins. The default output voltages can be externally set in 
the adjustable version or factory programmable to a wide range 
of preset values in the fixed voltage version.  
TYPICAL APPLICATION CIRCUIT 
AGND
VIN3
EN2
EN3
EN4
VIN4
EN1
VIN1
PWM
PSM/PWM
2.3V TO
5.5V
SW1
FB1
R2
R1
VOUT1
PGND1
MODE
C5
10µF
V
OUT1
 AT
800mA
V
OUT2
 AT
800mA
V
OUT3
 AT
300mA
V
OUT4
 AT
300mA
L1  1µH
EN1
BUCK1
MODE
C3
1µF
C2
4.7µF
C1
4.7µF
AVIN
C
AVIN
0.1µF
C4
1µF
VIN2
EN2
BUCK2
MODE
1.7V TO
5.5V
ON
OFF
ON
OFF
EN3
LDO1
(ANALOG)
ADP5037
HOUSEKEEPING
SW2
FB2
R4
R3
VOUT2
PGND2
C6
10µF
L2  1µH
FB3
R6
R5
VOUT3
C7
1µF
FB4
R8
R7
VOUT4
C8
1µF
EN4
LDO2
(DIGITAL)
0988
7-
00
1
 
Figure 1.