Analog Devices ADP1046 Evaluation Board ADP1046DC1-EVALZ ADP1046DC1-EVALZ データシート
製品コード
ADP1046DC1-EVALZ
UG-320
Evaluation Board User Guide
Rev. A | Page 44 of 48
APPENDIX III—REGISTER FILE (ADP1046_I2SF_032011.46R)
Table 10.
Register Address
Programmed Setting
Name
0x0
0x00
Fault Register 1
0x1
0x00
Fault Register 2
0x2
0x00
Fault Register 3
0x3
0x01
Fault Register 4
0x4
0x00
Latched Fault Register 1
0x5
0x00
Latched Fault Register 2
0x6
0x00
Latched Fault Register 3
0x7
0x61
Latched Fault Register 4
0x8
0x03
Fault Configuration Register 1
0x9
0x33
Fault Configuration Register 2
0xA
0x30
Fault Configuration Register 3
0xB
0x03
Fault Configuration Register 4
0xC
0x20
Fault Configuration Register 5
0xD
0x80
Fault Configuration Register 6
0xE
0x45
Flag configuration
0xF
0x23
Soft start flag blank
0x10
0x00
First Flag ID
0x11
0xE6
RTD current settings
0x12
0x00
HF ADC reading
0x13
0x3AFC
CS1 value
0x14
0xC7EC
ACSNS value
0x15
0xA0BC
VS1 voltage value
0x16
0xA098
VS2 voltage value
0x17
0xA000
VS3 voltage value
0x18
0x5644
CS2 value
0x19
0x00
CS2 × VS3 value
0x1A
0x5C34
RTD temperature value
0x1B
0x00
Read temperature
0x1C
0x00
RTD offset trim MSB
0x1D
0x00
Share bus value
0x1E
0x54
Modulation value
0x1F
0x00
Line impedance value
0x20
0x07
RTD offset trim setting (LSB)
0x21
0x84
CS1 gain trim
0x22
0xAD
CS1 accurate OCP limit
0x23
0x00
CS2 gain trim
0x24
0x00
CS2 analog offset trim
0x25
0x00
CS2 digital offset trim
0x26
0x6B
CS2 accurate OCP limit
0x27
0xE3
CS1/CS2 fast OCP settings
0x28
0x46
Volt-second balance gain setting
0x29
0x04
Share bus bandwidth
0x2A
0xF1
Share bus setting
0x2B
0x82
Temperature gain trim
0x2C
0x82
PSON/soft start settings
0x2D
0x5A
PGOOD debounce and pin polarity setting
0x2E
0x26
Modulation limit
0x2F
0xA0
OTP threshold
0x30
0x1C
OrFET
0x31
0xA0
VS3 voltage setting