Analog Devices ADP5040CP Evaluation Board ADP5040CP-1-EVALZ ADP5040CP-1-EVALZ データシート
製品コード
ADP5040CP-1-EVALZ
Micro PMU with 1.2 A Buck Regulator
and Two 300 mA LDOs
Data Sheet
Rev. A
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responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other
rights of third parties that may result from its use. Specifications subject to change without notice. No
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Trademarks and registered trademarks are the property of their respective owners.
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FEATURES
Input voltage range: 2.3 V to 5.5 V
One 1.2 A buck regulator
Two 300 mA LDOs
20-lead, 4 mm × 4 mm LFCSP package
Overcurrent and thermal protection
Soft start
Undervoltage lockout
Buck key specifications
One 1.2 A buck regulator
Two 300 mA LDOs
20-lead, 4 mm × 4 mm LFCSP package
Overcurrent and thermal protection
Soft start
Undervoltage lockout
Buck key specifications
Output voltage range: 0.8 V to 3.8 V
Current mode topology for excellent transient response
3 MHz operating frequency
Peak efficiency up to 96%
Uses tiny multilayer inductors and capacitors
Mode pin selects forced PWM or auto PWM/PSM modes
100% duty cycle low dropout mode
Current mode topology for excellent transient response
3 MHz operating frequency
Peak efficiency up to 96%
Uses tiny multilayer inductors and capacitors
Mode pin selects forced PWM or auto PWM/PSM modes
100% duty cycle low dropout mode
LDOs key specifications
Output voltage range: 0.8 V to 5.2 V
Low V
Low V
IN
from 1.7 V to 5.5 V
Stable with 2.2 µF ceramic output capacitors
High PSRR
Low output noise
Low dropout voltage
−40°C to +125°C junction temperature range
High PSRR
Low output noise
Low dropout voltage
−40°C to +125°C junction temperature range
GENERAL DESCRIPTION
combines one high performance buck regulator
and two low dropout regulators (LDO) in a small 20-lead
LFCSP to meet demanding performance and board space
LFCSP to meet demanding performance and board space
requirements.
The high switching frequency of the buck regulator enables the use
The high switching frequency of the buck regulator enables the use
of tiny multilayer external components and minimizes board space.
When the MODE pin is set to logic high, the buck regulator
operates in forced pulse width modulation (PWM) mode. When
the MODE pin is set to logic low, the buck regulator operates in
PWM mode when the load is around the nominal value. When
the load current falls below a predefined threshold the regulator
operates in power save mode (PSM) improving the light-load
efficiency. The low quiescent current, low dropout voltage, and
wide input voltage range of the
When the MODE pin is set to logic high, the buck regulator
operates in forced pulse width modulation (PWM) mode. When
the MODE pin is set to logic low, the buck regulator operates in
PWM mode when the load is around the nominal value. When
the load current falls below a predefined threshold the regulator
operates in power save mode (PSM) improving the light-load
efficiency. The low quiescent current, low dropout voltage, and
wide input voltage range of the
LDOs extend the
battery life of portable devices. The
LDOs maintain
a power supply rejection greater than 60 dB for frequencies as
is activated by a high level on
the respective enable pin. The output voltages of the regulators
are programmed though external resistor dividers to address a
are programmed though external resistor dividers to address a
variety of applications.
FUNCTIONAL BLOCK DIAGRAM
SW
C3
1µF
09665-
001
FB2
R4
R2
R1
R3
FB3
R3
R7
C2
2.2µF
2.2µF
C4
2.2µF
2.2µF
VOUT2
VOUT1
FB1
V
IN1
= 2.3V TO
5.5V
VIN1
EN1
VIN2
EN2
EN3
VIN3
V
IN3
= 1.7V
TO 5.5V
EN_LDO2
LDO2
(ANALOG)
BUCK
PGND
MODE
VOUT3
LDO1
(DIGITAL)
EN_LDO1
AVIN
AVIN
C5
4.7µF
V
IN2
= 1.7V
TO 5.5V
V
OUT1
AT
1.2A
V
OUT2
AT
300mA
V
OUT3
AT
300mA
C6
10µF
10µF
L1
1µH
C1
1µF
ON
OFF
ON
OFF
ON
OFF
AGND
EN_BK
PSM/PWM
FPWM
Figure 1.