Analog Devices AD9629 Evaluation Board AD9629-80EBZ AD9629-80EBZ データシート
製品コード
AD9629-80EBZ
12-Bit, 20 MSPS/40 MSPS/65 MSPS/80 MSPS,
1.8 V Analog-to-Digital Converter
AD9629
Rev. 0
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responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other
rights of third parties that may result from its use. Specifications subject to change without notice. No
license is granted by implication or otherwise under any patent or patent rights of Analog Devices.
Trademarks and registered trademarks are the property of their respective owners.
responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other
rights of third parties that may result from its use. Specifications subject to change without notice. No
license is granted by implication or otherwise under any patent or patent rights of Analog Devices.
Trademarks and registered trademarks are the property of their respective owners.
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Tel: 781.329.4700
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Fax: 781.461.3113
©2009 Analog Devices, Inc. All rights reserved.
FEATURES
1.8 V analog supply operation
1.8 V to 3.3 V output supply
SNR
1.8 V to 3.3 V output supply
SNR
71.3 dBFS at 9.7 MHz input
69.0 dBFS at 200 MHz input
69.0 dBFS at 200 MHz input
SFDR
95 dBc at 9.7 MHz input
83 dBc at 200 MHz input
83 dBc at 200 MHz input
Low power
45 mW at 20 MSPS
85 mW at 80 MSPS
85 mW at 80 MSPS
Differential input with 700 MHz bandwidth
On-chip voltage reference and sample-and-hold circuit
2 V p-p differential analog input
DNL = ±0.16 LSB
Serial port control options
On-chip voltage reference and sample-and-hold circuit
2 V p-p differential analog input
DNL = ±0.16 LSB
Serial port control options
Offset binary, gray code, or twos complement data format
Integer 1, 2, or 4 input clock divider
Built-in selectable digital test pattern generation
Energy-saving power-down modes
Data clock out with programmable clock and data alignment
Integer 1, 2, or 4 input clock divider
Built-in selectable digital test pattern generation
Energy-saving power-down modes
Data clock out with programmable clock and data alignment
APPLICATIONS
Communications
Diversity radio systems
Multimode digital receivers
Diversity radio systems
Multimode digital receivers
GSM, EDGE, W-CDMA, LTE, CDMA2000, WiMAX, TD-SCDMA
Smart antenna systems
Battery-powered instruments
Hand held scope meters
Portable medical imaging
Ultrasound
Radar/LIDAR
PET/SPECT imaging
Battery-powered instruments
Hand held scope meters
Portable medical imaging
Ultrasound
Radar/LIDAR
PET/SPECT imaging
FUNCTIONAL BLOCK DIAGRAM
SPI
MODE
CONTROLS
DIVIDE BY
1, 2, 4
REF
SELECT
VIN+
VIN–
VREF
SENSE
CLK+ CLK–
AVDD
GND
SDIO SCLK
CSB
PDWN
AD9629
DFS
MODE
D0 (LSB)
DCO
08
54
0-
0
01
D11 (MSB)
OR
CM
O
S
O
UT
P
U
T
BUF
F
E
R
ADC
CORE
PROGRAMMING DATA
RBIAS
VCM
DRVDD
Figure 1.
PRODUCT HIGHLIGHTS
1. The AD9629 operates from a single 1.8 V analog power
supply and features a separate digital output driver supply
to accommodate 1.8 V to 3.3 V logic families.
to accommodate 1.8 V to 3.3 V logic families.
2. The patented sample-and-hold circuit maintains excellent
performance for input frequencies up to 200 MHz and is
designed for low cost, low power, and ease of use.
designed for low cost, low power, and ease of use.
3. A standard serial port interface (SPI) supports various
product features and functions, such as data output format-
ting, internal clock divider, power-down, DCO and data
output (D11 to D0) timing and offset adjustments, and
voltage reference modes.
ting, internal clock divider, power-down, DCO and data
output (D11 to D0) timing and offset adjustments, and
voltage reference modes.
4. The AD9629 is packaged in a 32-lead RoHS compliant LFCSP
the
between 10-bit and 14-bit converters sampling from 20 MSPS
to 80 MSPS.
to 80 MSPS.