Analog Devices AD9257 Evaluation Board AD9257-65EBZ AD9257-65EBZ データシート
製品コード
AD9257-65EBZ
Octal, 14-Bit, 40/65 MSPS, Serial LVDS,
1.8 V Analog-to-Digital Converter
Data Sheet
Rev. A
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rights of third parties that may result from its use. Specifications subject to change without notice. No
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Trademarks and registered trademarks are the property of their respective owners.
responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other
rights of third parties that may result from its use. Specifications subject to change without notice. No
license is granted by implication or otherwise under any patent or patent rights of Analog Devices.
Trademarks and registered trademarks are the property of their respective owners.
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FEATURES
Low power: 55 mW per channel at 65 MSPS with scalable
power options
SNR = 75.5 dB (to Nyquist)
SFDR = 91.6 dBc (to Nyquist)
DNL = ±0.6 LSB (typical), INL = ±1.1 LSB (typical)
Serial LVDS (ANSI-644, default)
SFDR = 91.6 dBc (to Nyquist)
DNL = ±0.6 LSB (typical), INL = ±1.1 LSB (typical)
Serial LVDS (ANSI-644, default)
Low power, reduced signal option (similar to IEEE 1596.3)
Data and frame clock outputs
650 MHz full power analog bandwidth
2 V p-p input voltage range
1.8 V supply operation
Serial port control
650 MHz full power analog bandwidth
2 V p-p input voltage range
1.8 V supply operation
Serial port control
Full chip and individual channel power-down modes
Flexible bit orientation
Built-in and custom digital test pattern generation
Programmable clock and data alignment
Programmable output resolution
Standby mode
Flexible bit orientation
Built-in and custom digital test pattern generation
Programmable clock and data alignment
Programmable output resolution
Standby mode
APPLICATIONS
Medical imaging and nondestructive ultrasound
Portable ultrasound and digital beam-forming systems
Quadrature radio receivers
Diversity radio receivers
Optical networking
Test equipment
Portable ultrasound and digital beam-forming systems
Quadrature radio receivers
Diversity radio receivers
Optical networking
Test equipment
GENERAL DESCRIPTION
is an octal, 14-bit, 40 MSPS and 65 MSPS analog-
to-digital converter (ADC) with an on-chip sample-and-hold
circuit designed for low cost, low power, small size, and ease of
use. The product operates at a conversion rate of up to 65 MSPS
and is optimized for outstanding dynamic performance and low
power in applications where a small package size is critical.
circuit designed for low cost, low power, small size, and ease of
use. The product operates at a conversion rate of up to 65 MSPS
and is optimized for outstanding dynamic performance and low
power in applications where a small package size is critical.
The ADC requires a single 1.8 V power supply and LVPECL-/
CMOS-/LVDS-compatible sample rate clock for full performance
operation. No external reference or driver components are
required for many applications.
CMOS-/LVDS-compatible sample rate clock for full performance
operation. No external reference or driver components are
required for many applications.
The ADC automatically multiplies the sample rate clock for the
appropriate LVDS serial data rate. A data clock output (DCO) for
capturing data on the output and a frame clock output (FCO) for
signaling a new output byte are provided. Individual channel
power-down is supported and typically consumes less than
2 mW when all channels are disabled.
appropriate LVDS serial data rate. A data clock output (DCO) for
capturing data on the output and a frame clock output (FCO) for
signaling a new output byte are provided. Individual channel
power-down is supported and typically consumes less than
2 mW when all channels are disabled.
The ADC contains several features designed to maximize flexibility
and minimize system cost, such as programmable clock and data
and minimize system cost, such as programmable clock and data
FUNCTIONAL BLOCK DIAGRAM
ADC
14
SERIAL
LVDS
D+ A
D– A
D– A
VIN+ A
AVDD
AD9257
VIN– A
ADC
14
SERIAL
LVDS
D+ B
D– B
D– B
VIN+ B
VIN– B
VIN– B
ADC
14
SERIAL
LVDS
D+ C
D– C
D– C
VIN+ C
VIN– C
VIN– C
ADC
14
SERIAL
LVDS
D+ D
D– D
D– D
VIN+ D
VIN– D
VIN– D
ADC
14
SERIAL
LVDS
D+ E
D– E
D– E
VIN+ E
VIN– E
VIN– E
ADC
14
SERIAL
LVDS
D+ F
D– F
D– F
VIN+ F
VIN– F
VIN– F
ADC
14
SERIAL
LVDS
D+ G
D– G
D– G
VIN+ G
VIN– G
VIN– G
ADC
14
SERIAL
LVDS
DATA
RATE
RATE
MULTIPLIER
SERIAL PORT
INTERFACE
REF
SELECT
D+ H
FCO+
FCO–
FCO–
DCO+
DCO–
DCO–
D– H
VIN+ H
VIN– H
VIN– H
VREF
VCM
1.0V
SYNC
SENSE
PDWN
DRVDD
RBIAS
AGND
CSB
CLK+ CLK–
SDIO/
DFS
SCLK/
DTP
10
206
-0
01
Figure 1.
alignment and programmable digital test pattern generation. The
available digital test patterns include built-in deterministic and
pseudorandom patterns, along with custom user-defined test
patterns entered via the serial port interface (SPI).
available digital test patterns include built-in deterministic and
pseudorandom patterns, along with custom user-defined test
patterns entered via the serial port interface (SPI).
The
is available in an RoHS-compliant, 64-lead LFCSP.
It is specified over the industrial temperature range of −40°C
to +85°C. This product is protected by a U.S. patent.
to +85°C. This product is protected by a U.S. patent.
PRODUCT HIGHLIGHTS
1. Small Footprint. Eight ADCs are contained in a small,
space-saving package.
2. Low Power of 55 mW/Channel at 65 MSPS with Scalable
Power Options.
3. Ease of Use. A data clock output (DCO) is provided that
operates at frequencies of up to 455 MHz and supports
double data rate (DDR) operation.
double data rate (DDR) operation.
4. User Flexibility. The SPI control offers a wide range of
flexible features to meet specific system requirements.
5. Pin Compatible with the
(12-Bit Octal ADC).