Analog Devices AD5379 Evaluation Board EVAL-AD5379EBZ EVAL-AD5379EBZ データシート

製品コード
EVAL-AD5379EBZ
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40-Channel, 14-Bit, Parallel and
Serial Input, Bipolar Voltage-Output DAC
 
AD5379
 
 
Rev. B 
Information furnished by Analog Devices is believed to be accurate and reliable. However, no 
responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other 
rights of third parties that may result from its use. Specifications subject to change without notice. No 
license is granted by implication or otherwise under any patent or patent rights of Analog Devices. 
Trademarks and registered trademarks are the property of their respective owners. 
 
 
 
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: 781.329.4700 
www.analog.com
 
Fax: 781.461.3113 
©2004–2009 Analog Devices, Inc. All rights reserved. 
FEATURES 
40-channel DAC in 13 mm × 13 mm 108-lead CSPBGA 
Guaranteed monotonic to 14 bits 
Buffered voltage outputs 
Output voltage span of 3.5 V × V
REF
(+) 
Maximum output voltage span of 17.5 V 
System calibration function allowing user-programmable 
offset and gain 
Pseudo differential outputs relative to REFGND 
Clear function to user-defined REFGND (CLR pin) 
Simultaneous update of DAC outputs (LDAC pin) 
DAC increment/decrement mode 
Channel grouping and addressing features 
Interface options: 
Parallel interface  
DSP/microcontroller-compatible, 3-wire serial interface 
2.5 V to 5.5 V JEDEC-compliant digital levels 
SDO daisy-chaining option 
Power-on reset 
Digital reset (RESET pin and soft reset function) 
 
APPLICATIONS 
Level setting in automatic test equipment (ATE) 
Variable optical attenuators (VOA) 
Optical switches 
Industrial control systems 
 
FUNCTIONAL BLOCK DIAGRAM 
V
CC
V
DD
V
SS
AGND
RESET
POWER-ON
RESET
DGND
LDAC
V
BIAS
V
REF
1(+) V
REF
1(–) REFGND A1
VBIAS
DAC 0–1
DAC
REG
0–1
DAC
REG
2
DAC
REG
7
DAC
REG
8–9
INPUT
REG
0–1
INPUT
REG
2
INPUT
REG
7
INPUT
REG
8–9
DAC 2
DAC 7
DAC 8–9
AD5379
DCEN/WR
SYNC/CS
REG0
REG1
DB13
SCLK/DB12
DIN/DB11
DB0
A7
A0
SER/PAR
DIN
SCLK
SDO
FIFOEN
REFGND B1
REFGND B2
REFGND C1
REFGND C2
REFGND D1
REFGND D2
BUSY
V
REF
2(+) V
REF
2(–) REFGND A2
CLR
VOUT0
VOUT1
VOUT2
VOUT3
VOUT4
VOUT5
VOUT6
VOUT7
VOUT8
VOUT9
VOUT10
VOUT39
×4
14
/
14
/
14
/
14
/
14
/
14
/
14
/
14
/
14
/
14
/
14
/
14
/
14
/
14
/
m REG0–1
c REG0–1
m REG2
c REG2
m REG7
c REG7
m REG8–9
c REG8–9
14
/
14
/
14
/
14
/
14
/
14
/
14
/
FIFO
S
T
ATE
 MACHINE
INTE
RFACE
03165-001
 
Figure 1. 
 
AD5379—Protected by U.S. Patent No. 5,969,657