Analog Devices AD9653 Evaluation Board AD9653-125EBZ AD9653-125EBZ データシート
製品コード
AD9653-125EBZ
Quad, 16-Bit, 125 MSPS, Serial LVDS 1.8 V
Analog-to-Digital Converter
Data Sheet
Rev. 0
Information furnished by Analog Devices is believed to be accurate and reliable. However, no
responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other
rights of third parties that may result from its use. Specifications subject to change without notice. No
license is granted by implication or otherwise under any patent or patent rights of Analog Devices.
Trademarks and registered trademarks are the property of their respective owners.
responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other
rights of third parties that may result from its use. Specifications subject to change without notice. No
license is granted by implication or otherwise under any patent or patent rights of Analog Devices.
Trademarks and registered trademarks are the property of their respective owners.
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: 781.329.4700
Tel: 781.329.4700
Fax: 781.461.3113
©2012 Analog Devices, Inc. All rights reserved.
FEATURES
1.8 V supply operation
Low power: 164 mW per channel at 125 MSPS
SNR = 76.5 dBFS at 70 MHz (2.0 V p-p input span)
SNR = 77.5 dBFS at 70 MHz (2.6 V p-p input span)
SFDR = 90 dBc (to Nyquist, 2.0 V p-p input span)
DNL = ±0.7 LSB; INL = ±3.5 LSB (2.0 V p-p input span)
Serial LVDS (ANSI-644, default) and low power, reduced
Low power: 164 mW per channel at 125 MSPS
SNR = 76.5 dBFS at 70 MHz (2.0 V p-p input span)
SNR = 77.5 dBFS at 70 MHz (2.6 V p-p input span)
SFDR = 90 dBc (to Nyquist, 2.0 V p-p input span)
DNL = ±0.7 LSB; INL = ±3.5 LSB (2.0 V p-p input span)
Serial LVDS (ANSI-644, default) and low power, reduced
range option (similar to IEEE 1596.3)
650 MHz full power analog bandwidth
2 V p-p input voltage range (supports up to 2.6 V p-p)
Serial port control
2 V p-p input voltage range (supports up to 2.6 V p-p)
Serial port control
Full chip and individual channel power-down modes
Flexible bit orientation
Built-in and custom digital test pattern generation
Multichip sync and clock divider
Programmable output clock and data alignment
Standby mode
Flexible bit orientation
Built-in and custom digital test pattern generation
Multichip sync and clock divider
Programmable output clock and data alignment
Standby mode
APPLICATIONS
Medical ultrasound and MRI
High speed imaging
Quadrature radio receivers
Diversity radio receivers
Test equipment
High speed imaging
Quadrature radio receivers
Diversity radio receivers
Test equipment
GENERAL DESCRIPTION
verter (ADC) with an on-chip sample-and-hold circuit
designed for low cost, low power, small size, and ease of use.
The product operates at a conversion rate of up to 125 MSPS
and is optimized for outstanding dynamic performance and low
power in applications where a small package size is critical.
The ADC requires a single 1.8 V power supply and LVPECL-/
CMOS-/LVDS-compatible sample rate clock for full performance
operation. No external reference or driver components are
required for many applications.
The ADC automatically multiplies the sample rate clock for the
appropriate LVDS serial data rate. A data clock output (DCO) for
capturing data on the output and a frame clock output (FCO)
for signaling a new output byte are provided. Individual-channel
power-down is supported and typically consumes less than 2 mW
when all channels are disabled. The ADC contains several features
designed to maximize flexibility and minimize system cost, such
designed for low cost, low power, small size, and ease of use.
The product operates at a conversion rate of up to 125 MSPS
and is optimized for outstanding dynamic performance and low
power in applications where a small package size is critical.
The ADC requires a single 1.8 V power supply and LVPECL-/
CMOS-/LVDS-compatible sample rate clock for full performance
operation. No external reference or driver components are
required for many applications.
The ADC automatically multiplies the sample rate clock for the
appropriate LVDS serial data rate. A data clock output (DCO) for
capturing data on the output and a frame clock output (FCO)
for signaling a new output byte are provided. Individual-channel
power-down is supported and typically consumes less than 2 mW
when all channels are disabled. The ADC contains several features
designed to maximize flexibility and minimize system cost, such
FUNCTIONAL BLOCK DIAGRAM
Figure 1.
as programmable output clock and data alignment and digital
test pattern generation. The available digital test patterns
include built-in deterministic and pseudorandom patterns, along
with custom user-defined test patterns entered via the serial port
interface (SPI).
The
It is specified over the industrial temperature range of −40°C to
+85°C. This product is protected by a U.S. patent.
+85°C. This product is protected by a U.S. patent.
PRODUCT HIGHLIGHTS
1. Small Footprint.
Four ADCs are contained in a small, space-saving package.
2. Low power of 164 mW/channel at 125 MSPS with scalable
power options.
3. Pin compatible to the
12-bit quad ADC.
4. Ease of Use.
A data clock output (DCO) operates at frequencies of up to
500 MHz and supports double data rate (DDR) operation.
500 MHz and supports double data rate (DDR) operation.
5. User Flexibility.
The SPI control offers a wide range of flexible features to
meet specific system requirements.
meet specific system requirements.
AD9653
AVDD
PDWN
DRVDD
REF
SELECT
VIN–A
VIN+A
VIN–B
VIN+B
VIN–D
VIN+D
VIN–C
VIN+C
SENSE
AGND
SYN
C
VCM
VREF
D0–A
D0+A
D0–B
D0+B
D1–B
D1+B
D1–C
D1+C
D0–C
D0+C
D1–D
D1+D
DCO–
DCO+
D0–D
D0+D
FCO–
FCO+
D1–A
D1+A
C
L
K+
C
L
K–
C
S
B
S
D
IO/OLM
S
CL
K/
DT
P
RBIAS
PIPELINE
ADC
PIPELINE
ADC
PIPELINE
ADC
SERIAL
LVDS
DIGITAL
SERIALIZER
DIGITAL
SERIALIZER
DIGITAL
SERIALIZER
DIGITAL
SERIALIZER
CLOCK
MANAGEMENT
SERIAL PORT
INTERFACE
SERIAL
LVDS
SERIAL
LVDS
SERIAL
LVDS
SERIAL
LVDS
SERIAL
LVDS
SERIAL
LVDS
SERIAL
LVDS
PIPELINE
ADC
16
16
16
16
1V
10538-
001