Analog Devices ADP1879 Evaluation Board ADP1879-0.6-EVALZ ADP1879-0.6-EVALZ データシート
製品コード
ADP1879-0.6-EVALZ
ADP1878/ADP1879
Data
Sheet
Rev. B | Page 28 of 40
power dissipation across the internal LDO. Equation 3 shows the
power dissipation calculations for the integrated drivers and for
the internal LDO. Table 9 lists the thermal impedance for the
power dissipation calculations for the integrated drivers and for
the internal LDO. Table 9 lists the thermal impedance for the
, which are available in a 14-lead LFCSP_WD.
Table 9. Thermal Impedance for 14-Lead LFCSP_WD
Package Thermal
Impedance
14-Lead LFCSP_WD θ
JA
4-Layer Board
30°C/W
IC for a specified
high input voltage (V
IN
). Figure 85 illustrates the temperature
derating conditions for each available switching frequency for
low, typical, and high output setpoints for the 14-lead LFCSP_WD
package. All temperature derating criteria are based on a
maximum IC junction temperature of 125°C.
low, typical, and high output setpoints for the 14-lead LFCSP_WD
package. All temperature derating criteria are based on a
maximum IC junction temperature of 125°C.
Figure 85. Ambient Temperature vs. V
IN
,
4-Layer Evaluation Board, C
IN
= 4.3 nF (High-/Low-Side MOSFET)
The maximum junction temperature allowed for the
IC is 125°C. This means that the sum of the ambient
temperature (T
A
) and the rise in package temperature (T
R
), which is
caused by the thermal impedance of the package and the internal
power dissipation, should not exceed 125°C, as dictated by the
following expression:
power dissipation, should not exceed 125°C, as dictated by the
following expression:
T
J
= T
R
× T
A
(1)
where:
T
T
J
is the maximum junction temperature.
T
R
is the rise in package temperature due to the power
dissipated from within.
T
T
A
is the ambient temperature.
The rise in package temperature is directly proportional to its
thermal impedance characteristics. The following equation
represents this proportionality relationship:
thermal impedance characteristics. The following equation
represents this proportionality relationship:
T
R
= θ
JA
× P
DR(LOSS)
(2)
where:
θ
θ
JA
is the thermal resistance of the package from the junction to
the outside surface of the die, where it meets the surrounding air.
P
P
DR(LOSS)
is the overall power dissipated by the IC.
The bulk of the power dissipated is due to the gate capacitance of
the external MOSFETs and current running through the on-board
LDO. The power loss equations for the MOSFET drivers and
internal low dropout regulator (see the MOSFET Driver Loss
section and the Efficiency Consideration section) are:
the external MOSFETs and current running through the on-board
LDO. The power loss equations for the MOSFET drivers and
internal low dropout regulator (see the MOSFET Driver Loss
section and the Efficiency Consideration section) are:
P
DR(LOSS)
= [V
DR
× (f
SW
C
upperFET
V
DR
+ I
BIAS
)] +
[V
REG
× (f
SW
C
lowerFET
V
REG
+ I
BIAS
)] (3)
where:
C
C
upperFET
is the input gate capacitance of the high-side MOSFET.
C
lowerFET
is the input gate capacitance of the low-side MOSFET.
I
BIAS
is the dc current (2 mA) flowing into the high- and low-
side drivers.
V
V
DR
is the driver bias voltage (the low input voltage (V
REG
) minus
the rectifier drop (see Figure 83)).
V
V
REG
is the LDO output/bias voltage.
P
DISS(LDO)
= P
DR(LOSS)
+ (V
IN
– V
REG
) × (f
SW
× C
TOTAL
×
V
REG
+ I
BIAS
(4)
where P
DISS(LDO)
is the power dissipated through the pass device
in the LDO block across V
IN
and V
REG
.
P
DR(LOSS)
is the MOSFET driver loss.
V
IN
is the high voltage input.
V
REG
is the LDO output voltage and bias voltage.
C
TOTAL
is the C
GD
+ C
GS
of the external MOSFET.
I
BIAS
is the dc input bias current.
For example, if the external MOSFET characteristics are θ
JA
(14-lead LFCSP_WD) = 30°C/W, f
SW
= 300 kHz, I
BIAS
= 2 mA,
C
upperFET
= 3.3 nF, C
lowerFET
= 3.3 nF, V
DR
= 4.62 V, and V
REG
= 5.0 V,
then the power loss is
P
DR(LOSS)
= [V
DR
× (f
SWCupperFET
V
DR
+ I
BIAS
)] +
[V
REG
× (f
SWClowerFET
V
REG
+ I
BIAS
)]
= (4.62 × (300 × 10
3
× 3.3 × 10
−9
× 4.62 + 0.002)) +
(5.0 × (300 × 10
3
× 3.3 × 10
−9
× 5.0 + 0.002))
= 57.12 mW
P
DISS(LDO)
= (V
IN
– V
REG
) × (f
SW
× C
TOTAL
× V
REG
+ I
BIAS
) =
(13 V – 5 V) × (300 × 10
3
× 3.3 × 10
−9
× 5 + 0.002)
= 55.6 mW
P
DISS(TOTAL)
= P
DISS(LDO)
+ P
DR(LOSS)
= 77.13 mW + 55.6 mW
= 132.73 mW
130
90
100
110
120
5.5
19.0
17.5
16.0
14.5
13.0
11.5
10.0
8.5
7.0
M
A
X
IM
U
M
AL
L
O
W
A
B
L
E AM
BI
ENT
TE
M
P
E
R
A
T
U
R
E
(
°C
)
V
IN
(V)
09
44
1-
08
5
300kHz
600kHz
1MHz
600kHz
1MHz
V
OUT
= 0.8V
V
OUT
= 1.8V
V
OUT
= HIGH SETPOINT