Atmel Evaluation Kit AT91SAM9M10-G45-EK AT91SAM9M10-G45-EK データシート
製品コード
AT91SAM9M10-G45-EK
18
SAM9M10 [SUMMARY]
6355ES–ATARM–12-Mar-13
6.2.2
Matrix Slaves
Each Slave has its own arbiter, thus allowing a different arbitration per Slave to be programmed.
6.2.3
Masters to Slaves Access
All the Masters can normally access all the Slaves. However, some paths do not make sense, such as allowing access
from the Ethernet MAC to the internal peripherals. Thus, these paths are forbidden or simply not wired, and shown as “-”
in the following tables.
from the Ethernet MAC to the internal peripherals. Thus, these paths are forbidden or simply not wired, and shown as “-”
in the following tables.
The four DDR ports are connected differently according to the application device.
The user can disable the Video Decoder in the Video Mode Configuration Register (bit VDEC_SEL) in the Chip
Configuration User Interface.
Configuration User Interface.
z
When the
Video Decoder is not enabled (VDEC_SEL=0)
, the ARM instruction and data are respectively connected to
DDR Port 0 and DDR Port 1. The other masters share DDR Port 2 and DDR Port 3.
z
When the
Video Decoder is enabled (VDEC_SEL=1),
DDR Port 0 is dedicated to the video controller, and DDR Port 1
to the LCD controller. The remaining masters share DDR Port 2 and DDR Port 3.
Table 6-2.
List of Bus Matrix Slaves
Slave 0
Internal SRAM
Slave 1
Internal ROM
USB OHCI
USB EHCI
UDP High Speed RAM
LCD User Interface
Video Decoder
Slave 2
DDR Port 0
Slave 3
DDR Port 1
Slave 4
DDR Port 2
Slave 5
DDR Port 3
Slave 6
External Bus Interface
Slave 7
Internal Peripherals