Atmel Evaluation Kit AT91SAM9M10-G45-EK AT91SAM9M10-G45-EK データシート
製品コード
AT91SAM9M10-G45-EK
31
SAM9M10 [SUMMARY]
6355ES–ATARM–12-Mar-13
8.3
Reset Controller
The Reset Controller is based on two Power-on-Reset cells, one on VDDBU and one on VDDCORE.
The Reset Controller is capable to return to the software the source of the last reset, either a general reset (VDDBU
rising), a wake-up reset (VDDCORE rising), a software reset, a user reset or a watchdog reset.
rising), a wake-up reset (VDDCORE rising), a software reset, a user reset or a watchdog reset.
The Reset Controller controls the internal resets of the system and the NRST pin output. It is capable to shape a reset
signal for the external devices, simplifying to a minimum connection of a push-button on the NRST pin to implement a
manual reset.
signal for the external devices, simplifying to a minimum connection of a push-button on the NRST pin to implement a
manual reset.
The configuration of the Reset Controller is saved as supplied on VDDBU.
8.4
Shut Down Controller
The Shut Down Controller is supplied on VDDBU and allows a software-controllable shut down of the system through the
pin SHDN. An input change of the WKUP pin or an alarm releases the SHDN pin, and thus wakes up the system power
supply.
pin SHDN. An input change of the WKUP pin or an alarm releases the SHDN pin, and thus wakes up the system power
supply.
8.5
Clock Generator
The Clock Generator is made up of:
z
One Low Power 32768 Hz Slow Clock Oscillator with bypass mode
z
One Low-Power RC oscillator
z
One 12 MHz Main Oscillator, which can be bypassed
z
One 400 to 800 MHz programmable PLLA, capable to provide the clock MCK to the processor and to the
peripherals. This PLL has an input divider to offer a wider range of output frequencies from the 12 MHz input, the
only limitation being the lowest input frequency shall be higher or equal to 2 MHz.
peripherals. This PLL has an input divider to offer a wider range of output frequencies from the 12 MHz input, the
only limitation being the lowest input frequency shall be higher or equal to 2 MHz.
The USB Device and Host HS Clocks are provided by a the dedicated UTMI PLL (UPLL) embedded in the UTMI macro.
Figure 8-2.
Clock Generator Block Diagram
Power
Management
Controller
XIN
XO
UT
Main Cloc
MAINCK
MAINCK
Control
Status
PLLA and
Divider
PLLA Cloc
PLLACK
PLLACK
12M Main
O
scillator
UPLL
O
n Chip
RC O
SC
Slow Cloc
SLCK
SLCK
XIN32
XO
UT32
Slow Cloc
O
scillator
Cloc Generator
RCEN
UPLLCK
O
SCSEL
O
SC32EN
O
SC32BYP