Atmel Evaluation Kit AT91SAM9M10-G45-EK AT91SAM9M10-G45-EK データシート
製品コード
AT91SAM9M10-G45-EK
34
SAM9M10 [SUMMARY]
6355ES–ATARM–12-Mar-13
Figure 8-4.
SAM9M10 Power Management Controller Block Diagram
8.7.1
Main Application Modes
The Power Management Controller provides 3 main application modes.
8.7.1.1 Normal Mode
z
PLLA and UPLL are running respectively at 400 MHz and 480 MHz
z
USB Device High Speed and Host EHCI High Speed operations are allowed
z
Full Speed OHCI input clock is UPLLCK, USBDIV is 9 (division by 10)
z
System Input clock is PLLACK, PCK is 400 MHz
z
MDIV is ‘11’, MCK is 133 MHz
z
DDR2 can be used at up to 133 MHz
8.7.1.2 USB HS and LP-DDR Mode
z
Only UPLL is running at 480 MHz, PLLA power consumption is saved
z
USB Device High Speed and Host EHCI High Speed operations are allowed
z
Full Speed OHCI input clock is UPLLCK, USBDIV is 9 (division by 10)
z
System Input clock is UPLLCK, Prescaler is 2, PCK is 240 MHz
z
MDIV is ‘01’, MCK is 120 MHz
z
Only LP-DDR can be used at up to 120 MHz
8.7.1.3 No UDP HS, UHP FS and DDR2 Mode
z
Only PLLA is running at 384 MHz, UPLL power consumption is saved
UHP48M
UHP12M
SysClk DDR
MCK
periph_clk[..]
int
SLCK
MAINCK
PLLACK
Prescaler
/1,/2,/4,.../64
PCK
Processor
Clock
Controller
Master Clock Controller
Peripherals
Clock Controller
ON/OFF
/1 /2 /3 /4
SLCK
MAINCK
Prescaler
/1,/2,/4,...,/64
Programmable Clock Controller
pck[..]
ON/OFF
UPLLCK
/1,/2
UPLLCK
USB
OHCI
USBDIV+1
/4
USB
EHCI
USBS
Divider
X /1 /1.5 /2