Atmel ARM-Based Evaluation Kit AT91SAM9N12-EK AT91SAM9N12-EK データシート
製品コード
AT91SAM9N12-EK
Tightly-Coupled Memory Interface
ARM DDI0198D
Copyright © 2001-2003 ARM Limited. All rights reserved.
5-25
Figure 5-16 TCM subsystem that uses wait states for nonsequential accesses
The address and chip-select inputs to the ROM are pipelined with respect to the
ARM926EJ-S TCM interface outputs. An address incrementer is used to generate
sequential addresses. The output of the incrementer is captured at the end of every cycle
where the ROM CS chip select is active. The address source for the ROM is switched
over to the registered version of IRADDR when a nonsequential access occurs.
ARM926EJ-S TCM interface outputs. An address incrementer is used to generate
sequential addresses. The output of the incrementer is captured at the end of every cycle
where the ROM CS chip select is active. The address source for the ROM is switched
over to the registered version of IRADDR when a nonsequential access occurs.
Figure 5-17 on page 5-26 shows the timing of the ROM address, chip-select, and read
data relative to the ARM926EJ-S TCM interface signals. The address supplied to the
ROM can either be behind, in sync with, or ahead of IRADDR, depending on the type
of memory access and the presence of idle cycles.
data relative to the ARM926EJ-S TCM interface signals. The address supplied to the
ROM can either be behind, in sync with, or ahead of IRADDR, depending on the type
of memory access and the presence of idle cycles.
ROM
IRRD[31:0]
IRADDR[17:0]
IRCS
IRSEQ
IRWAIT
CS
A
RD
ARM926EJ-S
1
0
0
EN
+1