Atmel ARM-Based Evaluation Kit AT91SAM9N12-EK AT91SAM9N12-EK データシート
製品コード
AT91SAM9N12-EK
Memory Management Unit
3-4
Copyright © 2001-2003 ARM Limited. All rights reserved.
ARM DDI0198D
3.1.3
MMU program accessible registers
Table 3-1 shows the CP15 registers that are used in conjunction with page table
descriptors stored in memory to determine the operation of the MMU.
descriptors stored in memory to determine the operation of the MMU.
All the CP15 MMU registers, except c8, contain state that can be read using MRC
instructions, and written using MCR instructions. Registers c5 and c6 are also written
by the MMU during an abort. Writing to c8 causes the MMU to perform a TLB
operation, to manipulate TLB entries. This register is write-only.
instructions, and written using MCR instructions. Registers c5 and c6 are also written
by the MMU during an abort. Writing to c8 causes the MMU to perform a TLB
operation, to manipulate TLB entries. This register is write-only.
The CP15 registers are described in Chapter 2 Programmer’s Model.
Table 3-1 MMU program-accessible CP15 registers
Register
Bits
Register description
Control register
c1
c1
M, A, S, R
Contains bits to enable the MMU (M bit), enable data address alignment
checks (A bit), and to control the access protection scheme (S bit and R
bit).
checks (A bit), and to control the access protection scheme (S bit and R
bit).
Translation table
base register c2
base register c2
[31:14]
Holds the physical address of the base of the translation table
maintained in main memory. This base address must be on a 16KB
boundary.
maintained in main memory. This base address must be on a 16KB
boundary.
Domain access
control register
c3
control register
c3
[31:0]
Comprises 16 two-bit fields. Each field defines the access control
attributes for one of 16 domains (D15 to D0).
attributes for one of 16 domains (D15 to D0).
Fault status
registers, IFSR
and DFSR, c5
registers, IFSR
and DFSR, c5
[7:0]
Indicates the cause of a Data or Prefetch Abort, and the domain number
of the aborted access, when an abort occurs. Bits [7:4] specify which of
the 16 domains (D15 to D0) was being accessed when a fault occurred.
Bits [3:0] indicate the type of access being attempted. The value of all
other bits is Unpredictable. The encoding of these bits is shown in
Table 3-9 on page 3-22.
of the aborted access, when an abort occurs. Bits [7:4] specify which of
the 16 domains (D15 to D0) was being accessed when a fault occurred.
Bits [3:0] indicate the type of access being attempted. The value of all
other bits is Unpredictable. The encoding of these bits is shown in
Table 3-9 on page 3-22.
Fault address
register c6
register c6
[31:0]
Holds the MVA associated with the access that caused the Data Abort.
See Table 3-9 on page 3-22 for details of the address stored for each
type of fault. The ARM9EJ-S register R14_abt holds the VA associated
with a Prefetch Abort.
See Table 3-9 on page 3-22 for details of the address stored for each
type of fault. The ARM9EJ-S register R14_abt holds the VA associated
with a Prefetch Abort.
TLB operations
register c8
register c8
[31:0]
This register is used to perform TLB maintenance operations. These are
either invalidating all the (unpreserved) entries in the TLB, or
invalidating a specific entry.
either invalidating all the (unpreserved) entries in the TLB, or
invalidating a specific entry.
TLB lockdown
register c10
register c10
[28:26] and
[0]
[0]
Enables specific page table entries to be locked into the TLB. Locking
entries in the TLB guarantees that accesses to the locked page or section
can proceed without incurring the time penalty of a TLB miss. This
enables the execution latency for time-critical pieces of code such as
interrupt handlers to be minimized.
entries in the TLB guarantees that accesses to the locked page or section
can proceed without incurring the time penalty of a TLB miss. This
enables the execution latency for time-critical pieces of code such as
interrupt handlers to be minimized.