Atmel Evaluation Kit AT91SAM9G25-EK AT91SAM9G25-EK データシート

309

SAM9G25 [DATASHEET]

11032C–ATARM–25-Jan-13

Note:

1.

A switch, NFD0_ON_D16, enables the user to select NAND Flash path on D0-D7 or D16-D24 depending on 
memory power supplies. This switch is located in the EBICSA register in the Bus Matrix user interface.

The pins used for interfacing the External Bus Interface may be multiplexed with the PIO lines. The programmer must
first program the PIO controller to assign the External Bus Interface pins to their peripheral function. If I/O lines of the
External Bus Interface are not used by the application, they can be used for other purposes by the PIO Controller.

The EBI transfers data between the internal AHB Bus (handled by the Bus Matrix) and the external memories or
peripheral devices. It controls the waveforms and the parameters of the external address, data and control buses and is
composed of the following elements:

z

Static Memory Controller (SMC)

z

DDR2/SDRAM Controller (DDR2SDRC)

z

Programmable Multibit ECC Controller (PMECC)

z

A chip select assignment feature that assigns an AHB address space to the external devices

z

A multiplex controller circuit that shares the pins between the different Memory Controllers

z

Programmable NAND Flash support logic

The EBI offers a complete set of control signals that share the 32-bit data lines, the address lines of up to 26 bits and the
control signals through a multiplex logic operating in function of the memory area requests.

Multiplexing is specifically organized in order to guarantee the maintenance of the address and output control lines at a
stable state while no external access is being performed. Multiplexing is also designed to respect the data float times
defined in the Memory Controllers. Furthermore, refresh cycles of the DDR2 and SDRAM are executed independently by
the DDR2SDR Controller without delaying the other external Memory Controller accesses.

The EBI_CSA registers in the Chip Configuration User Interface enable on-chip pull-up and pull-down resistors on data
bus lines not multiplexed with the PIO Controller lines. The pull-down resistors are enabled after reset. The bits,
EBIx_DBPUC and EBI_DBPDC, control the pull-up and pull-down resistors on the D0 - D15 lines. Pull-up or pull-down
resistors on the D16 - D31 lines can be performed by programming the appropriate PIO controller.

The EBI I/Os accept two drive levels, HIGH and LOW. This allows to avoid overshoots and give the best performance
according to the bus load and external memories.

The slew rates are determined by programming EBI_DRIVE field in the Chip Configuration registers located in the Matrix
User Interface.

CAS

VDDIOM

CAS

CAS

–

SDWE

VDDIOM

WE

WE

–

Pxx

VDDNF

–

–

CE

Pxx

VDDNF

–

–

RDY

DDR2/LPDDR

SDR/LPSDR

NAND Flash