Atmel Evaluation Kit AT91SAM9G25-EK AT91SAM9G25-EK データシート

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SAM9G25 [DATASHEET]

11032C–ATARM–25-Jan-13

The following configuration has to be performed:

z

Assign EBI_CS1 to the DDR2 controller by setting the bit EBI_CS1A in the EBI Chip Select Register located in the 
bus matrix memory space.

z

Initialize the DDR2 Controller depending on the LP-DDR device and system bus frequency.

The LP-DDR initialization sequence is described in the section “Low-power DDR1-SDRAM Initialization” in “DDR/SDR
SDRAM Controller (DDRSDRC)”.

In this case VDDNF can be different from VDDIOM. NAND Flash device can be 3.3V or 1.8V and wired on D16-D31 data
bus. NFD0_ON_D16 is to be set to 1.