Atmel Evaluation Kit AT91SAM9G25-EK AT91SAM9G25-EK データシート
製品コード
AT91SAM9G25-EK
566
SAM9G25 [DATASHEET]
11032C–ATARM–25-Jan-13
• ERR_FLUSH: Bank Flush Error Clear
0 = No effect.
1 = Clear the ERR_FLUSH flags of UDPHS_EPTSTAx.
32.7.19 UDPHS Endpoint Status Register (Control, Bulk, Interrupt Endpoints)
Name: UDPHS_EPTSTAx
[x=0..6]
Access:
Read-only
This register view is relevant only if EPT_TYPE=0x0, 0x2 or 0x3 in
• FRCESTALL: Stall Handshake Request
0 = No effect.
1 = If set a STALL answer will be done to the host for the next handshake.
This bit is reset by hardware upon received SETUP.
• TOGGLESQ_STA: Toggle Sequencing
Toggle Sequencing:
–
IN Endpoint:
It indicates the PID Data Toggle that will be used for the next packet sent. This is not relative to
the current bank.
– CONTROL and OUT endpoint:
These bits are set by hardware to indicate the PID data of the current bank:
Notes: 1. In OUT transfer, the Toggle information is meaningful only when the current bank is busy (Received OUT Data = 1).
2. These bits are updated for OUT transfer:
-
A new data has been written into the current bank.
-
The user has just cleared the Received OUT Data bit to switch to the next bank.
3. This field is reset to DATA1 by the UDPHS_EPTCLRSTAx register TOGGLESQ bit, and by UDPHS_EPTCTLDISx
(disable endpoint).
31
30
29
28
27
26
25
24
SHRT_PCKT
BYTE_COUNT
23
22
21
20
19
18
17
16
BYTE_COUNT
BUSY_BANK_STA
CURBK_CTLDIR
15
14
13
12
11
10
9
8
NAK_OUT
NAK_IN
STALL_SNT
RX_SETUP
TXRDY
TX_COMPLT
RXRDY_TXKL
ERR_OVFLW
7
6
5
4
3
2
1
0
TOGGLESQ_STA
FRCESTALL
–
–
–
–
–
Value
Name
Description
0
DATA0
DATA0
1
DATA1
DATA1
2
DATA2
Reserved for High Bandwidth Isochronous Endpoint
3
MDATA
Reserved for High Bandwidth Isochronous Endpoint