Atmel Evaluation Kit AT91SAM9G25-EK AT91SAM9G25-EK データシート
製品コード
AT91SAM9G25-EK
57
SAM9G25 [DATASHEET]
11032C–ATARM–25-Jan-13
A specific register, the Debug Unit Chip ID Register, gives information about the product version and its internal
configuration.
configuration.
The device Debug Unit Chip ID value is 0x819A_05A1
on 32-bit width.
For further details on the Debug Unit, see the Debug Unit section.
10.6.5 IEEE 1149.1 JTAG Boundary Scan
IEEE 1149.1 JTAG Boundary Scan allows pin-level access independent of the device packaging technology.
IEEE 1149.1 JTAG Boundary Scan is enabled when JTAGSEL is high. The SAMPLE, EXTEST and BYPASS functions
are implemented. In ICE debug mode, the ARM processor responds with a non-JTAG chip ID that identifies the
processor to the ICE system. This is not IEEE 1149.1 JTAG-compliant.
are implemented. In ICE debug mode, the ARM processor responds with a non-JTAG chip ID that identifies the
processor to the ICE system. This is not IEEE 1149.1 JTAG-compliant.
It is not possible to switch directly between JTAG and ICE operations. A chip reset must be performed after JTAGSEL is
changed.
changed.
A Boundary-scan Descriptor Language (BSDL) file is provided to set up test.