Atmel Evaluation Kit AT91SAM9G25-EK AT91SAM9G25-EK データシート

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SAM9G25 [DATASHEET]

11032C–ATARM–25-Jan-13

The ADC is based on a 10-bit Analog-to-Digital Converter (ADC) managed by an ADC Controller. Refer to the Block
Diagram: 

. It also integrates a 12-to-1 analog multiplexer, making possible the analog-to-digital conversions

of 12

 

analog lines. The conversions extend from 0V to ADVREF. The ADC supports an 8-bit or 10-bit resolution mode,

and conversion results are reported in a common register for all channels, as well as in a channel-dedicated register.

Software trigger, external trigger on rising edge of the ADTRG pin or internal triggers from Timer Counter output(s) are
configurable.

The comparison circuitry allows automatic detection of values below a threshold, higher than a threshold, in a given
range or outside the range, thresholds and ranges being fully configurable.

The ADC also integrates a Sleep Mode and a conversion sequencer and connects with a DMA  channel. These features
reduce both power consumption and processor intervention.

 A whole set of reference voltages is generated internally from a single external reference voltage node that may be
equal to the analog supply voltage. An external decoupling capacitance is required for noise filtering.

Finally, the user can configure ADC timings, such as Startup Time and Tracking Time.