Atmel Evaluation Kit AT91SAM9X35-EK AT91SAM9X35-EK データシート
製品コード
AT91SAM9X35-EK
450
SAM9X35 [DATASHEET]
11055E–ATARM–10-Mar-2014
31.4 Functional Description
31.4.1 Basic Definitions
Source peripheral: Device on an AMBA layer from where the DMAC reads data, which is then stored in the channel
FIFO. The source peripheral teams up with a destination peripheral to form a channel.
FIFO. The source peripheral teams up with a destination peripheral to form a channel.
Destination peripheral: Device to which the DMAC writes the stored data from the FIFO (previously read from the
source peripheral).
source peripheral).
Memory: Source or destination that is always “ready” for a DMAC transfer and does not require a handshaking interface
to interact with the DMAC.
to interact with the DMAC.
Programmable Arbitration Policy: Modified Round Robin and Fixed Priority are available by means of the ARB_CFG
bit in the Global Configuration Register (DMAC_GCFG). The fixed priority is linked to the channel number. The highest
DMAC channel number has the highest priority.
bit in the Global Configuration Register (DMAC_GCFG). The fixed priority is linked to the channel number. The highest
DMAC channel number has the highest priority.
Channel: Read/write datapath between a source peripheral on one configured AMBA layer and a destination peripheral
on the same or different AMBA layer that occurs through the channel FIFO. If the source peripheral is not memory, then
a source handshaking interface is assigned to the channel. If the destination peripheral is not memory, then a destination
handshaking interface is assigned to the channel. Source and destination handshaking interfaces can be assigned
dynamically by programming the channel registers.
on the same or different AMBA layer that occurs through the channel FIFO. If the source peripheral is not memory, then
a source handshaking interface is assigned to the channel. If the destination peripheral is not memory, then a destination
handshaking interface is assigned to the channel. Source and destination handshaking interfaces can be assigned
dynamically by programming the channel registers.
Master interface: DMAC is a master on the AHB bus reading data from the source and writing it to the destination over
the AHB bus.
the AHB bus.
Slave interface: The APB interface over which the DMAC is programmed. The slave interface in practice could be on
the same layer as any of the master interfaces or on a separate layer.
the same layer as any of the master interfaces or on a separate layer.
Handshaking interface: A set of signal registers that conform to a protocol and handshake between the DMAC and
source or destination peripheral to control the transfer of a single or chunk transfer between them. This interface is used
to request, acknowledge, and control a DMAC transaction. A channel can receive a request through one of two types of
handshaking interface: hardware or software.
source or destination peripheral to control the transfer of a single or chunk transfer between them. This interface is used
to request, acknowledge, and control a DMAC transaction. A channel can receive a request through one of two types of
handshaking interface: hardware or software.
Hardware handshaking interface: Uses hardware signals to control the transfer of a single or chunk transfer between
the DMAC and the source or destination peripheral.
the DMAC and the source or destination peripheral.
Software handshaking interface: Uses software registers to control the transfer of a single or chunk transfer between
the DMAC and the source or destination peripheral. No special DMAC handshaking signals are needed on the I/O of the
peripheral. This mode is useful for interfacing an existing peripheral to the DMAC without modifying it.
the DMAC and the source or destination peripheral. No special DMAC handshaking signals are needed on the I/O of the
peripheral. This mode is useful for interfacing an existing peripheral to the DMAC without modifying it.
Flow controller: The device (either the DMAC or source/destination peripheral) that determines the length of and
terminates a DMAC buffer transfer. If the length of a buffer is known before enabling the channel, then the DMAC should
be programmed as the flow controller. If the length of a buffer is not known prior to enabling the channel, the source or
destination peripheral needs to terminate a buffer transfer. In this mode, the peripheral is the flow controller.
terminates a DMAC buffer transfer. If the length of a buffer is known before enabling the channel, then the DMAC should
be programmed as the flow controller. If the length of a buffer is not known prior to enabling the channel, the source or
destination peripheral needs to terminate a buffer transfer. In this mode, the peripheral is the flow controller.
Transfer hierarchy:
illustrates the hierarchy between DMAC transfers, buffer transfers, chunk
or single, and AMBA transfers (single or burst) for non-memory peripherals.
shows the transfer
hierarchy for memory.