Atmel Xplained Pro Evaluation Kit ATSAM4E-XPRO ATSAM4E-XPRO データシート

SAM4E [DATASHEET]

Atmel-11157D-ATARM-SAM4E16-SAM4E8-Datasheet_12-Jun-14

1204

An Ethernet encoded 802.1Q VLAN tag looks like this:

The VLAN tag is inserted at the 13th byte of the frame adding an extra four bytes to the frame. To support these
extra four bytes, the GMAC can accept frame lengths up to 1536 bytes by setting bit 8 in the Network
Configuration Register.

If the VID (VLAN identifier) is null (0x000) this indicates a priority-tagged frame.

The following bits in the receive buffer descriptor status word give information about VLAN tagged frames:-



Bit 21 set if receive frame is VLAN tagged (i.e., type ID of 0x8100).



Bit 20 set if receive frame is priority tagged (i.e., type ID of 0x8100 and null VID). (If bit 20 is set, bit 21 will be 
set also.)



Bit 19, 18 and 17 set to priority if bit 21 is set.



Bit 16 set to CFI if bit 21 is set.

The GMAC can be configured to reject all frames except VLAN tagged frames by setting the discard non-VLAN
frames bit in the Network Configuration Register.

IEEE 1588 is a standard for precision time synchronization in local area networks. It works with the exchange of
special Precision Time Protocol (PTP) frames. The PTP messages can be transported over IEEE 802.3/Ethernet,
over Internet Protocol Version 4 or over Internet Protocol Version 6 as described in the annex of IEEE P1588.D2.1.

GMAC output pins indicate the message time-stamp point (asserted on the start packet delimiter and de-asserted
at end of frame) for all frames and the passage of PTP event frames (asserted when a PTP event frame is
detected and de-asserted at end of frame).

Synchronization between master and slave clocks is a two stage process.

First, the offset between the master and slave clocks is corrected by the master sending a sync frame to the slave
with a follow up frame containing the exact time the sync frame was sent. Hardware assist modules at the master
and slave side detect exactly when the sync frame was sent by the master and received by the slave. The slave
then corrects its clock to match the master clock.

Second, the transmission delay between the master and slave is corrected. The slave sends a delay request
frame to the master which sends a delay response frame in reply. Hardware assist modules at the master and
slave side detect exactly when the delay request frame was sent by the slave and received by the master. The
slave will now have enough information to adjust its clock to account for delay. For example, if the slave was
assuming zero delay, the actual delay will be half the difference between the transmit and receive time of the delay
request frame (assuming equal transmit and receive times) because the slave clock will be lagging the master
clock by the delay time already.

The time-stamp is taken when the message time-stamp point passes the clock time-stamp point. For Ethernet the
message time-stamp point is the SFD and the clock time-stamp point is the MII interface. (The IEEE 1588
specification refers to sync and delay_req messages as event messages as these require time-stamping. Follow
up, delay response and management messages do not require time-stamping and are referred to as general
messages.)

1588 version 2 defines two additional PTP event messages. These are the peer delay request (Pdelay_Req) and
peer delay response (Pdelay_Resp) messages. These messages are used to calculate the delay on a link. Nodes

0x8100

First 3 bits priority, then CFI bit, last 12 bits VID