Atmel Xplained Pro Evaluation Kit ATSAM4E-XPRO ATSAM4E-XPRO データシート

SAM4E [DATASHEET]

Atmel-11157D-ATARM-SAM4E16-SAM4E8-Datasheet_12-Jun-14

1214

Transmit data is read from areas of data (the buffers) in system memory. These buffers are listed in another data
structure that also resides in main memory. This data structure (Transmit Buffer Queue) is a sequence of
descriptor entries as defined in 

The Transmit Buffer Queue Pointer Register points to this data structure. 

To create this list of buffers:

1.

Allocate a number (N) of buffers of between 1 and 2047 bytes of data to be transmitted in system memory. Up to 
128 buffers per frame are allowed.

2.

Allocate an area 8N bytes for the transmit buffer descriptor list in system memory and create N entries in this 
list. Mark all entries in this list as owned by GMAC, i.e., bit 31 of word 1 set to 0.

3.

Mark the last descriptor in the queue with the wrap bit (bit 30 in word 1 set to 1).

4.

Write address of transmit buffer descriptor list and control information to GMAC register transmit buffer 
queue pointer.

5.

The transmit circuits can then be enabled by writing to the Network Control Register.

The GMAC register pair hash address and the four Specific Address Register-pairs must be written with the
required values. Each register pair comprises a bottom register and top register with the bottom register being
written first. The address matching is disabled for a particular register pair after the bottom register has been
written and re-enabled when the top register is written. Each register pair may be written at any time, regardless of
whether the receive circuits are enabled or disabled.

As an example, to set Specific Address Register 1 to recognize destination address 21:43:65:87:A9:CB, the
following values are written to Specific Address Register 1 bottom and Specific Address Register 1 top:



Specific Address Register 1 bottom bits 31:0 (0x98): 8765_4321 hex.



Specific Address Register 1 top bits 31:0 (0x9C): 0000_CBA9 hex.

The PHY Maintenance Register is implemented as a shift register. Writing to the register starts a shift operation
which is signalled as complete when bit two is set in the Network Status Register (about 2000 MCK cycles later
when bits [18:16] are set to 010 in the Network Configuration Register). An interrupt is generated as this bit is set.

During this time, the MSB of the register is output on the MDIO pin and the LSB updated from the MDIO pin with
each Management Data Clock (MDC) cycle. This causes the transmission of a PHY management frame on MDIO.
See section 22.2.4.5 of the IEEE 802.3 standard.

Reading during the shift operation will return the current contents of the shift register. At the end of the
management operation the bits will have shifted back to their original locations. For a read operation the data bits
are updated with data read from the PHY. It is important to write the correct values to the register to ensure a valid
PHY management frame is produced.

The Management Data Clock (MDC) should not toggle faster than 2.5 MHz (minimum period of 400 ns), as defined
by the IEEE 802.3 standard. MDC is generated by dividing down MCK. Three bits in the Network Configuration
Register determine by how much MCK should be divided to produce MDC.

There are 18 interrupt conditions that are detected within the GMAC. These are ORed to make a single interrupt.
Depending on the overall system design this may be passed through a further level of interrupt collection (interrupt
controller). On receipt of the interrupt signal, the CPU enters the interrupt handler. Refer to the device interrupt
controller documentation to identify that it is the GMAC that is generating the interrupt. To ascertain which
interrupt, read the Interrupt Status Register. Note that in the default configuration this register will clear itself after
being read, though this may be configured to be write-one-to-clear if desired.