Atmel Xplained Pro Evaluation Kit ATSAM4E-XPRO ATSAM4E-XPRO データシート
製品コード
ATSAM4E-XPRO
SAM4E [DATASHEET]
Atmel-11157D-ATARM-SAM4E16-SAM4E8-Datasheet_12-Jun-14
1360
If a software reset is performed (SWRST bit in AFEC_CR) or after power up (or wake-up from Backup mode), the
calibration data in the AFEC memory is lost.
calibration data in the AFEC memory is lost.
Changing the AFEC running mode (in the AFEC_CR) does not affect the calibration data.
Changing the AFEC reference voltage (ADVREF pin) requires a new calibration sequence.
For calibration time, offset and gain error after calibration, refer to the 12-bit AFEC electrical characteristics of the
product datasheet.
product datasheet.
45.6.15 Buffer Structure
The PDC read channel is triggered each time a new data is stored in the AFEC_LCDR. The same structure of data
is repeatedly stored in the AFEC_LCDR each time a trigger event occurs. Depending on user mode of operation
(AFEC_MR, AFEC_CHSR, AFEC_SEQR1, AFEC_SEQR2) the structure differs. Each data transferred to PDC
buffer, carried on a half-word (16-bit), consists of last converted data right aligned and when TAG is set in the
AFEC_EMR, data is carried on a word buffer (32-bit) and CHNB field carries the channel number thus allowing an
easier post-processing in the PDC buffer or better checking the PDC buffer integrity.
is repeatedly stored in the AFEC_LCDR each time a trigger event occurs. Depending on user mode of operation
(AFEC_MR, AFEC_CHSR, AFEC_SEQR1, AFEC_SEQR2) the structure differs. Each data transferred to PDC
buffer, carried on a half-word (16-bit), consists of last converted data right aligned and when TAG is set in the
AFEC_EMR, data is carried on a word buffer (32-bit) and CHNB field carries the channel number thus allowing an
easier post-processing in the PDC buffer or better checking the PDC buffer integrity.
45.6.16 Fault Output
The AFE Controller internal fault output is directly connected to PWM fault input. Fault output may be asserted
according to the configuration of AFEC_EMR (Extended Mode Register) and AFEC_CWR (Compare Window
Register) and converted values. When the Compare occurs, the AFEC fault output generates a pulse of one
Master Clock Cycle to the PWM fault input. This fault line can be enabled or disabled within PWM. Should it be
activated and asserted by the AFE Controller, the PWM outputs are immediately placed in a safe state (pure
combinational path). Note that the AFEC fault output connected to the PWM is not the COMPE bit. Thus the Fault
Mode (FMOD) within the PWM configuration must be FMOD = 1.
according to the configuration of AFEC_EMR (Extended Mode Register) and AFEC_CWR (Compare Window
Register) and converted values. When the Compare occurs, the AFEC fault output generates a pulse of one
Master Clock Cycle to the PWM fault input. This fault line can be enabled or disabled within PWM. Should it be
activated and asserted by the AFE Controller, the PWM outputs are immediately placed in a safe state (pure
combinational path). Note that the AFEC fault output connected to the PWM is not the COMPE bit. Thus the Fault
Mode (FMOD) within the PWM configuration must be FMOD = 1.
45.6.17 Register Write Protection
To prevent any single software error from corrupting AFEC behavior, certain registers in the address space can be
write-protected by setting the WPEN bit in the
write-protected by setting the WPEN bit in the
(AFEC_WPMR).
If a write access to a write-protected register is detected, the WPVS flag in the
(AFEC_WPSR) is set and the field WPVSRC indicates the register in which the write access has been
attempted.
The WPVS flag is automatically cleared by reading the AFEC_WPSR.
The protected registers are: