Atmel Xplained Pro Evaluation Kit ATSAM4E-XPRO ATSAM4E-XPRO データシート
製品コード
ATSAM4E-XPRO
355
SAM4E [DATASHEET]
Atmel-11157D-ATARM-SAM4E16-SAM4E8-Datasheet_12-Jun-14
17.4
Functional Description
The Watchdog Timer is used to prevent system lock-up if the software becomes trapped in a deadlock. It is
supplied with VDDCORE. It restarts with initial values on processor reset.
supplied with VDDCORE. It restarts with initial values on processor reset.
The watchdog is built around a 12-bit down counter, which is loaded with the value defined in the field WDV of the
Mode register (WDT_MR). The Watchdog Timer uses the slow clock divided by 128 to establish the maximum
watchdog period to be 16 seconds (with a typical slow clock of 32.768 kHz).
Mode register (WDT_MR). The Watchdog Timer uses the slow clock divided by 128 to establish the maximum
watchdog period to be 16 seconds (with a typical slow clock of 32.768 kHz).
After a processor reset, the value of WDV is 0xFFF, corresponding to the maximum value of the counter with the
external reset generation enabled (field WDRSTEN at 1 after a backup reset). This means that a default watchdog
is running at reset, i.e., at power-up. The user must either disable it (by setting the WDDIS bit in WDT_MR) if he
does not expect to use it or must reprogram it to meet the maximum watchdog period the application requires.
external reset generation enabled (field WDRSTEN at 1 after a backup reset). This means that a default watchdog
is running at reset, i.e., at power-up. The user must either disable it (by setting the WDDIS bit in WDT_MR) if he
does not expect to use it or must reprogram it to meet the maximum watchdog period the application requires.
If the watchdog is restarted by writing into the Control register (WDT_CR), WDT_MR must not be programmed
during a period of time of three slow clock periods following the WDT_CR write access. In any case, programming
a new value in WDT_MR automatically initiates a restart instruction.
during a period of time of three slow clock periods following the WDT_CR write access. In any case, programming
a new value in WDT_MR automatically initiates a restart instruction.
WDT_MR can be written only once. Only a processor reset resets it. Writing WDT_MR reloads the timer with the
newly programmed mode parameters.
newly programmed mode parameters.
In normal operation, the user reloads the watchdog at regular intervals before the timer underflow occurs, by
writing WDT_CR with the bit WDRSTT to 1. The watchdog counter is then immediately reloaded from WDT_MR
and restarted, and the slow clock 128 divider is reset and restarted. WDT_CR is write-protected. As a result,
writing WDT_CR without the correct hard-coded key has no effect. If an underflow does occur, the “wdt_fault”
signal to the Reset Controller is asserted if the bit WDRSTEN is set in WDT_MR. Moreover, the bit WDUNF is set
in the Status register (WDT_SR).
writing WDT_CR with the bit WDRSTT to 1. The watchdog counter is then immediately reloaded from WDT_MR
and restarted, and the slow clock 128 divider is reset and restarted. WDT_CR is write-protected. As a result,
writing WDT_CR without the correct hard-coded key has no effect. If an underflow does occur, the “wdt_fault”
signal to the Reset Controller is asserted if the bit WDRSTEN is set in WDT_MR. Moreover, the bit WDUNF is set
in the Status register (WDT_SR).
To prevent a software deadlock that continuously triggers the watchdog, the reload of the watchdog must occur
while the watchdog counter is within a window between 0 and WDD, WDD is defined in WDT_MR.
while the watchdog counter is within a window between 0 and WDD, WDD is defined in WDT_MR.
Any attempt to restart the watchdog while the watchdog counter is between WDV and WDD results in a watchdog
error, even if the watchdog is disabled. The bit WDERR is updated in WDT_SR and the “wdt_fault” signal to the
Reset Controller is asserted.
error, even if the watchdog is disabled. The bit WDERR is updated in WDT_SR and the “wdt_fault” signal to the
Reset Controller is asserted.
Note that this feature can be disabled by programming a WDD value greater than or equal to the WDV value. In
such a configuration, restarting the Watchdog Timer is permitted in the whole range [0; WDV] and does not
generate an error. This is the default configuration on reset (the WDD and WDV values are equal).
such a configuration, restarting the Watchdog Timer is permitted in the whole range [0; WDV] and does not
generate an error. This is the default configuration on reset (the WDD and WDV values are equal).
The status bits WDUNF (Watchdog Underflow) and WDERR (Watchdog Error) trigger an interrupt, provided the bit
WDFIEN is set in WDT_MR. The signal “wdt_fault” to the Reset Controller causes a watchdog reset if the
WDRSTEN bit is set as already explained in the Reset Controller documentation. In this case, the processor and
the Watchdog Timer are reset, and the WDERR and WDUNF flags are reset.
WDFIEN is set in WDT_MR. The signal “wdt_fault” to the Reset Controller causes a watchdog reset if the
WDRSTEN bit is set as already explained in the Reset Controller documentation. In this case, the processor and
the Watchdog Timer are reset, and the WDERR and WDUNF flags are reset.
If a reset is generated or if WDT_SR is read, the status bits are reset, the interrupt is cleared, and the “wdt_fault”
signal to the reset controller is deasserted.
signal to the reset controller is deasserted.
Writing WDT_MR reloads and restarts the down counter.
While the processor is in debug state or in idle mode, the counter may be stopped depending on the value
programmed for the bits WDIDLEHLT and WDDBGHLT in WDT_MR.
programmed for the bits WDIDLEHLT and WDDBGHLT in WDT_MR.