Atmel Xplained Pro Evaluation Kit ATSAM4E-XPRO ATSAM4E-XPRO データシート
製品コード
ATSAM4E-XPRO
SAM4E [DATASHEET]
Atmel-11157D-ATARM-SAM4E16-SAM4E8-Datasheet_12-Jun-14
556
28.14 Asynchronous Page Mode
The SMC supports asynchronous burst reads in page mode, providing that the page mode is enabled in the
SMC_MODE register (PMEN field). The page size must be configured in the SMC_MODE register (PS field) to 4,
8, 16 or 32 bytes.
SMC_MODE register (PMEN field). The page size must be configured in the SMC_MODE register (PS field) to 4,
8, 16 or 32 bytes.
The page defines a set of consecutive bytes into memory. A 4-byte page (resp. 8-, 16-, 32-byte page) is always
aligned to 4-byte boundaries (resp. 8-, 16-, 32-byte boundaries) of memory. The MSB of data address defines the
address of the page in memory, the LSB of address define the address of the data in the page as detailed in
aligned to 4-byte boundaries (resp. 8-, 16-, 32-byte boundaries) of memory. The MSB of data address defines the
address of the page in memory, the LSB of address define the address of the data in the page as detailed in
.
With page mode memory devices, the first access to one page (t
pa
) takes longer than the subsequent accesses to
the page (t
sa
. When in page mode, the SMC enables the user to define different read
timings for the first access within one page, and next accesses within the page.
Note:
1.
“A” denotes the address bus of the memory device.
28.14.1 Protocol and Timings in Page Mode
shows the NRD and NCS timings in page mode access.
Figure 28-31. Page Mode Read Protocol (Address MSB and LSB are defined in
)
The NRD and NCS signals are held low during all read transfers, whatever the programmed values of the setup
and hold timings in the User Interface may be. Moreover, the NRD and NCS timings are identical. The pulse length
of the first access to the page is defined with the NCS_RD_PULSE field of the SMC_PULSE register. The pulse
length of subsequent accesses within the page are defined using the NRD_PULSE parameter.
and hold timings in the User Interface may be. Moreover, the NRD and NCS timings are identical. The pulse length
of the first access to the page is defined with the NCS_RD_PULSE field of the SMC_PULSE register. The pulse
length of subsequent accesses within the page are defined using the NRD_PULSE parameter.
Table 28-5.
Page Address and Data Address within a Page
Page Size
Page Address
Data Address in the Page
4 bytes
A[23:2]
A[1:0]
8 bytes
A[23:3]
A[2:0]
16 bytes
A[23:4]
A[3:0]
32 bytes
A[23:5]
A[4:0]
A[MSB]
NCS
MCK
NRD
D[7:0]
NCS_RD_PULSE
NRD_PULSE
NRD_PULSE
tsa
tpa
tsa
A[LSB]