Atmel Xplained Pro Evaluation Kit ATSAM4E-XPRO ATSAM4E-XPRO データシート
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製品コード
ATSAM4E-XPRO
SAM4E [DATASHEET]
Atmel-11157D-ATARM-SAM4E16-SAM4E8-Datasheet_12-Jun-14
570
29.
Clock Generator
29.1
Description
The Clock Generator user interface is embedded within the Power Management Controller and is described in
. However, the Clock Generator registers are
named CKGR_.
29.2
Embedded Characteristics
The Clock Generator is made up of:
A low-power 32768 Hz slow clock oscillator with bypass mode
A low-power RC oscillator
A 3 to 20 MHz crystal or ceramic resonator-based oscillator, which can be bypassed.
A factory-programmed fast RC oscillator. Three output frequencies can be selected: 4/8/12 MHz. By default
4 MHz is selected.
4 MHz is selected.
A 80 to 240 MHz programmable PLL (input from 3 to 32 MHz), capable of providing the clock MCK to the
processor and to the peripherals.
processor and to the peripherals.
Write Protected Registers
It provides the following clocks:
SLCK, the slow clock, which is the only permanent clock within the system.
MAINCK is the output of the main clock oscillator selection: either the crystal or ceramic resonator-based
oscillator or 4/8/12 MHz fast RC oscillator.
oscillator or 4/8/12 MHz fast RC oscillator.
PLLACK is the output of the divider and 80 to 240 MHz programmable PLL (PLLA).