Atmel Xplained Pro Evaluation Kit ATSAM4E-XPRO ATSAM4E-XPRO データシート
製品コード
ATSAM4E-XPRO
723
SAM4E [DATASHEET]
Atmel-11157D-ATARM-SAM4E16-SAM4E8-Datasheet_12-Jun-14
Figure 34-8.
Input Change Interrupt Timings When No Additional Interrupt Modes
34.5.11 I/O Lines Lock
When an I/O line is controlled by a peripheral (particularly the Pulse Width Modulation Controller PWM), it can
become locked by the action of this peripheral via an input of the PIO Controller. When an I/O line is locked, the
write of the corresponding bit in PIO_PER, PIO_PDR, PIO_MDER, PIO_MDDR, PIO_PUDR, PIO_PUER,
PIO_ABCDSR1 and PIO_ABCDSR2 is discarded in order to lock its configuration. The user can know at anytime
which I/O line is locked by reading the PIO Lock Status register (PIO_LOCKSR). Once an I/O line is locked, the
only way to unlock it is to apply a hardware reset to the PIO Controller.
become locked by the action of this peripheral via an input of the PIO Controller. When an I/O line is locked, the
write of the corresponding bit in PIO_PER, PIO_PDR, PIO_MDER, PIO_MDDR, PIO_PUDR, PIO_PUER,
PIO_ABCDSR1 and PIO_ABCDSR2 is discarded in order to lock its configuration. The user can know at anytime
which I/O line is locked by reading the PIO Lock Status register (PIO_LOCKSR). Once an I/O line is locked, the
only way to unlock it is to apply a hardware reset to the PIO Controller.
34.5.12 Programmable I/O Delays
The PIO interface consists of a series of signals driven by peripherals or directly by software. The simultaneous
switching outputs on these busses may lead to a peak of current in the internal and external power supply lines.
switching outputs on these busses may lead to a peak of current in the internal and external power supply lines.
In order to reduce the current peak in such cases, additional propagation delays can be adjusted independently for
pad buffers by means of configuration registers, PIO_DELAY.
pad buffers by means of configuration registers, PIO_DELAY.
The additional programmable delays for each supporting range from 0 to
-
ns (Worst Case PVT). The delay can
differ between I/Os supporting this feature. Delay can be modified per programming for each I/O. The minimal
additional delay that can be programmed on a PAD supporting this feature is 1/16 of the maximum programmable
delay.
additional delay that can be programmed on a PAD supporting this feature is 1/16 of the maximum programmable
delay.
Only pads PA26-PA27-PA30-PA31 can be configured.
When programming 0x0 in fields, no delay is added (reset value) and the propagation delay of the pad buffers is
the inherent delay of the pad buffer. When programming 0xF in fields, the propagation delay of the corresponding
pad is maximal.
the inherent delay of the pad buffer. When programming 0xF in fields, the propagation delay of the corresponding
pad is maximal.
Peripheral clock
Pin Level
Read PIO_ISR
APB Access
PIO_ISR
APB Access