Atmel Xplained Pro Evaluation Kit ATSAM4E-XPRO ATSAM4E-XPRO データシート
製品コード
ATSAM4E-XPRO
867
SAM4E [DATASHEET]
Atmel-11157D-ATARM-SAM4E16-SAM4E8-Datasheet_12-Jun-14
37.4
Product Dependencies
37.4.1 I/O Lines
The UART pins are multiplexed with PIO lines. The user must first configure the corresponding PIO Controller to
enable I/O line operations of the UART.
enable I/O line operations of the UART.
37.4.2 Power Management
The UART clock can be controlled through the Power Management Controller (PMC). In this case, the user must
first configure the PMC to enable the UART clock. Usually, the peripheral identifier used for this purpose is 1.
first configure the PMC to enable the UART clock. Usually, the peripheral identifier used for this purpose is 1.
37.4.3 Interrupt Source
The UART interrupt line is connected to one of the interrupt sources of the Interrupt Controller. Interrupt handling
requires programming of the Interrupt Controller before configuring the UART.
requires programming of the Interrupt Controller before configuring the UART.
37.5
UART Operations
The UART operates in asynchronous mode only and supports only 8-bit character handling (with parity). It has no
clock pin.
clock pin.
The UART is made up of a receiver and a transmitter that operate independently, and a common baud rate
generator. Receiver timeout and transmitter time guard are not implemented. However, all the implemented
features are compatible with those of a standard USART.
generator. Receiver timeout and transmitter time guard are not implemented. However, all the implemented
features are compatible with those of a standard USART.
37.5.1 Baud Rate Generator
The baud rate generator provides the bit period clock named baud rate clock to both the receiver and the
transmitter.
transmitter.
The baud rate clock is the peripheral clock divided by 16 times the value (CD) written in the Baud Rate Generator
register (UART_BRGR). If UART_BRGR is set to 0, the baud rate clock is disabled and the UART remains
inactive. The maximum allowable baud rate is peripheral clock divided by 16. The minimum allowable baud rate is
peripheral clock divided by (16 x 65536).
register (UART_BRGR). If UART_BRGR is set to 0, the baud rate clock is disabled and the UART remains
inactive. The maximum allowable baud rate is peripheral clock divided by 16. The minimum allowable baud rate is
peripheral clock divided by (16 x 65536).
Table 37-2.
I/O Lines
Instance
Signal
I/O Line
Peripheral
UART0
URXD0
PA9
A
UART0
UTXD0
PA10
A
UART1
URXD1
PA5
C
UART1
UTXD1
PA6
C
Baud Rate
f
peripheral clock
16
CD
×
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