Atmel Xplained Pro Evaluation Kit ATSAM4E-XPRO ATSAM4E-XPRO データシート

953

SAM4E [DATASHEET]

Atmel-11157D-ATARM-SAM4E16-SAM4E8-Datasheet_12-Jun-14

US_MAN

0x400A0050 (0), 0x400A4050 (1)

Read/Write

This register can only be written if the WPEN bit is cleared in “USART Write Protection Mode Register” on page 955.



0: The transmitter preamble pattern generation is disabled

1–15: The preamble length is TX_PL x Bit Period



The following values assume that TX_MPOL field is not set: 



0: Logic zero is coded as a zero-to-one transition, Logic one is coded as a one-to-zero transition.

1: Logic zero is coded as a one-to-zero transition, Logic one is coded as a zero-to-one transition.



0: The receiver preamble pattern detection is disabled

1–15: The detected preamble length is RX_PL x Bit Period



The following values assume that RX_MPOL field is not set:

31

30

29

28

27

26

25

24

–

DRIFT

ONE

RX_MPOL

–

–

RX_PP

23

22

21

20

19

18

17

16

–

–

–

–

RX_PL

15

14

13

12

11

10

9

8

–

–

–

TX_MPOL

–

–

TX_PP

7

6

5

4

3

2

1

0

–

–

–

–

TX_PL

0

ALL_ONE

The preamble is composed of ‘1’s

1

ALL_ZERO

The preamble is composed of ‘0’s

2

ZERO_ONE

The preamble is composed of ‘01’s

3

ONE_ZERO

The preamble is composed of ‘10’s

00

ALL_ONE

The preamble is composed of ‘1’s