Atmel ARM-Based Evaluation Kit AT91SAM9N12-EK AT91SAM9N12-EK データシート

製品コード
AT91SAM9N12-EK
ページ / 1104
811
SAM9N12/SAM9CN11/SAM9CN12 [DATASHEET]
11063K–ATARM–05-Nov-13
• CHMODE: Channel Mode  
• CPOL: SPI Clock Polarity
Applicable if USART operates in SPI Mode (Slave or Master, USART_MODE = 0xE or 0xF):
0: The inactive state value of SPCK is logic level zero.
1: The inactive state value of SPCK is logic level one.
CPOL is used to determine the inactive state value of the serial clock (SPCK). It is used with CPHA to produce the required 
clock/data relationship between master and slave devices.
• WRDBT: Wait Read Data Before Transfer
0: The character transmission starts as soon as a character is written into US_THR register (assuming TXRDY was set).
1: The character transmission starts when a character is written and only if RXRDY flag is cleared (Receiver Holding Register has 
been read).
Value
Name
Description
0
NORMAL
Normal Mode
1
AUTOMATIC
Automatic Echo. Receiver input is connected to the TXD pin. 
2
LOCAL_LOOPBACK
Local Loopback. Transmitter output is connected to the Receiver Input.
3
REMOTE_LOOPBACK
Remote Loopback. RXD pin is internally connected to the TXD pin.